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| author | Andre Przywara <andre.przywara@arm.com> | 2017-04-26 01:32:39 +0100 |
|---|---|---|
| committer | Jagan Teki <jagan@openedev.com> | 2017-05-17 23:19:57 +0530 |
| commit | 45e2d067669aee876badb23600e2145e562a961d (patch) | |
| tree | 2545de688531994ca788972c048bcafaa9f084c3 /tools/mksunxiboot.c | |
| parent | 85c07a5a379e5874aef0e5a0560536a2e6fa6114 (diff) | |
| download | u-boot-45e2d067669aee876badb23600e2145e562a961d.tar.gz | |
tools: mksunxiboot: allow larger SPL binaries
mksunxiboot limits the size of the resulting SPL binaries to pretty
conservative values to cover all SoCs and all boot media (NAND).
It turns out that we have limit checks in place in the build process,
so mksunxiboot can be relaxed and allow packaging binaries up to the
actual 32KB the mask boot ROM actually imposes.
This allows to have a bigger SPL, which is crucial for AArch64 builds.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'tools/mksunxiboot.c')
| -rw-r--r-- | tools/mksunxiboot.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c index 0f0b003a83..111d74a3ee 100644 --- a/tools/mksunxiboot.c +++ b/tools/mksunxiboot.c @@ -48,8 +48,8 @@ int gen_check_sum(struct boot_file_head *head_p) #define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1) #define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) -#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */ -#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head)) +#define SUNXI_SRAM_SIZE 0x8000 /* SoC with smaller size are limited before */ +#define SRAM_LOAD_MAX_SIZE (SUNXI_SRAM_SIZE - sizeof(struct boot_file_head)) /* * BROM (at least on A10 and A20) requires NAND-images to be explicitly aligned |