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| author | Dalon Westergreen <dalon.westergreen@intel.com> | 2021-03-01 20:04:16 +0800 |
|---|---|---|
| committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2021-03-08 10:59:12 +0800 |
| commit | 9773ebcfbca23c7d6fe1dc202913b005bc23cc89 (patch) | |
| tree | 56352355ea1a5d62c636ec436dd197cdae684386 /scripts/Makefile.spl | |
| parent | 8a3244d0baf691db1b59ff99e6815f53d1acafb1 (diff) | |
| download | u-boot-9773ebcfbca23c7d6fe1dc202913b005bc23cc89.tar.gz | |
Makefile: socfpga: Add target to generate hex output for combined spl and dtb
Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel
SOCFPGA SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex"
is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It
combines the spl image and dtb. "u-boot-spl-dtb.hex" is needed to
generate the final configuration bitstream for Intel SOCFPGA SOC64
devices.
Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Diffstat (limited to 'scripts/Makefile.spl')
| -rw-r--r-- | scripts/Makefile.spl | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index ea4e045769..1fd63efdfd 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -229,6 +229,8 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) INPUTS-y += $(obj)/$(SPL_BIN).sfp endif +INPUTS-$(CONFIG_TARGET_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex + ifdef CONFIG_ARCH_SUNXI INPUTS-y += $(obj)/sunxi-spl.bin @@ -389,6 +391,11 @@ $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \ -n $(CONFIG_DEFAULT_DEVICE_TREE) +OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) + +$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE + $(call if_changed,objcopy) + $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mkimage) |