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authorpekon gupta <pekon@ti.com>2014-07-22 16:03:24 +0530
committerTom Rini <trini@ti.com>2014-08-25 10:48:12 -0400
commit9352697aa060e9b1b5d891e4490fdfa6f5ba6114 (patch)
tree3b99b784f58c2f384f4fe18e562b6911d8f130f9 /include
parent54a97d2849979acd84a0475486edf0d0c18e47c7 (diff)
downloadu-boot-9352697aa060e9b1b5d891e4490fdfa6f5ba6114.tar.gz
board/ti/dra7xx: add support for parallel NOR
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
Diffstat (limited to 'include')
-rw-r--r--include/configs/dra7xx_evm.h38
1 files changed, 38 insertions, 0 deletions
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 10c88dcf96..d7d6d304c6 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -193,4 +193,42 @@
#endif
#endif /* !CONFIG_NAND */
+/* Parallel NOR Support */
+#if defined(CONFIG_NOR)
+/* NOR: device related configs */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
+/* #define CONFIG_INIT_IGNORE_ERROR */
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
+ "128k(NOR.SPL)," \
+ "128k(NOR.SPL.backup1)," \
+ "128k(NOR.SPL.backup2)," \
+ "128k(NOR.SPL.backup3)," \
+ "256k(NOR.u-boot-spl-os)," \
+ "1m(NOR.u-boot)," \
+ "128k(NOR.u-boot-env)," \
+ "128k(NOR.u-boot-env.backup1)," \
+ "8m(NOR.kernel)," \
+ "-(NOR.rootfs)"
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#endif
+#endif /* NOR support */
+
#endif /* __CONFIG_DRA7XX_EVM_H */