Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING

zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation

mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode

nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params

scsi:
- convert ceva sata to UCLASS_AHCI

timer:
- Add Cadence TTC for ZynqMP r5

watchdog:
- Minor cadence driver cleanup

6 files changed, 129 insertions, 55 deletions

diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h
new file mode 100644
index 0000000000..05105e5d44
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_r5.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+ */
+
+#ifndef __CONFIG_ZYNQMP_R5_H
+#define __CONFIG_ZYNQMP_R5_H
+
+#define CONFIG_EXTRA_ENV_SETTINGS
+
+/* CPU clock */
+#define CONFIG_CPU_FREQ_HZ	500000000
+
+/* Serial drivers */
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+# define CONFIG_ENV_SIZE	(128 << 10)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Boot configuration */
+#define CONFIG_SYS_LOAD_ADDR		0 /* default? */
+
+#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MALLOC_LEN		0x1400000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* 0x0 - 0x40 is used for placing exception vectors */
+#define CONFIG_SYS_MEMTEST_START	0x40
+#define CONFIG_SYS_MEMTEST_END		0x100
+#define CONFIG_SYS_MEMTEST_SCRATCH	0
+
+#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */
diff --git a/include/configs/xilinx_zynqmp_zc1275_revB.h b/include/configs/xilinx_zynqmp_zc1275_revB.h
new file mode 100644
index 0000000000..4cebe21006
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1275_revB.h
@@ -0,0 +1,16 @@
+/*
+ * Configuration for Xilinx ZynqMP zc1275 RevB
+ *
+ * (C) Copyright 2018 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1275_REVB_H
+#define __CONFIG_ZYNQMP_ZC1275_REVB_H
+
+#define CONFIG_ZYNQ_SDHCI1
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1275_REVB_H */
diff --git a/include/image.h b/include/image.h
index cd13cd242a..df701e3470 100644
--- a/include/image.h
+++ b/include/image.h
@@ -268,6 +268,7 @@ enum {
 	IH_TYPE_RKSPI,			/* Rockchip SPI image		*/
 	IH_TYPE_ZYNQIMAGE,		/* Xilinx Zynq Boot Image */
 	IH_TYPE_ZYNQMPIMAGE,		/* Xilinx ZynqMP Boot Image */
+	IH_TYPE_ZYNQMPBIF,		/* Xilinx ZynqMP Boot Image (bif) */
 	IH_TYPE_FPGA,			/* FPGA Image */
 	IH_TYPE_VYBRIDIMAGE,	/* VYBRID .vyb Image */
 	IH_TYPE_TEE,            /* Trusted Execution Environment OS Image */
diff --git a/include/sdhci.h b/include/sdhci.h
index 1e0c92c4cb..bef37df982 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -166,6 +166,11 @@
 #define  SDHCI_CAN_64BIT	BIT(28)
 
 #define SDHCI_CAPABILITIES_1	0x44
+#define  SDHCI_SUPPORT_SDR50	0x00000001
+#define  SDHCI_SUPPORT_SDR104	0x00000002
+#define  SDHCI_SUPPORT_DDR50	0x00000004
+#define  SDHCI_USE_SDR50_TUNING	0x00002000
+
 #define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
 #define  SDHCI_CLOCK_MUL_SHIFT	16
 
@@ -220,6 +225,7 @@
 #define SDHCI_QUIRK_BROKEN_HISPD_MODE	BIT(5)
 #define SDHCI_QUIRK_WAIT_SEND_CMD	(1 << 6)
 #define SDHCI_QUIRK_USE_WIDE8		(1 << 8)
+#define SDHCI_QUIRK_NO_1_8_V		(1 << 9)
 
 /* to make gcc happy */
 struct sdhci_host;
@@ -242,6 +248,8 @@ struct sdhci_ops {
 	void	(*set_control_reg)(struct sdhci_host *host);
 	void	(*set_ios_post)(struct sdhci_host *host);
 	void	(*set_clock)(struct sdhci_host *host, u32 div);
+	int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+	void (*set_delay)(struct sdhci_host *host);
 };
 
 struct sdhci_host {
diff --git a/include/zynqmp_tap_delay.h b/include/zynqmp_tap_delay.h
new file mode 100644
index 0000000000..b07e3e0692
--- /dev/null
+++ b/include/zynqmp_tap_delay.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx ZynqMP SoC Tap Delay Programming
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef __ZYNQMP_TAP_DELAY_H__
+#define __ZYNQMP_TAP_DELAY_H__
+
+#ifdef CONFIG_ARCH_ZYNQMP
+void zynqmp_dll_reset(u8 deviceid);
+void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank);
+#else
+inline void zynqmp_dll_reset(u8 deviceid) {}
+inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {}
+#endif
+
+#endif
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 9c63c016f5..cdfd8a205a 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -11,23 +11,18 @@
 
 #include <xilinx.h>
 
-#if defined(CONFIG_FPGA_ZYNQPL)
 extern struct xilinx_fpga_op zynq_op;
-# define FPGA_ZYNQPL_OPS	&zynq_op
-#else
-# define FPGA_ZYNQPL_OPS	NULL
-#endif
 
-#define XILINX_ZYNQ_7007S	0x3
-#define XILINX_ZYNQ_7010	0x2
-#define XILINX_ZYNQ_7012S	0x1c
-#define XILINX_ZYNQ_7014S	0x8
-#define XILINX_ZYNQ_7015	0x1b
-#define XILINX_ZYNQ_7020	0x7
-#define XILINX_ZYNQ_7030	0xc
-#define XILINX_ZYNQ_7035	0x12
-#define XILINX_ZYNQ_7045	0x11
-#define XILINX_ZYNQ_7100	0x16
+#define XILINX_ZYNQ_XC7Z007S	0x3
+#define XILINX_ZYNQ_XC7Z010	0x2
+#define XILINX_ZYNQ_XC7Z012S	0x1c
+#define XILINX_ZYNQ_XC7Z014S	0x8
+#define XILINX_ZYNQ_XC7Z015	0x1b
+#define XILINX_ZYNQ_XC7Z020	0x7
+#define XILINX_ZYNQ_XC7Z030	0xc
+#define XILINX_ZYNQ_XC7Z035	0x12
+#define XILINX_ZYNQ_XC7Z045	0x11
+#define XILINX_ZYNQ_XC7Z100	0x16
 
 /* Device Image Sizes */
 #define XILINX_XC7Z007S_SIZE	16669920/8
@@ -41,45 +36,29 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_XC7Z045_SIZE	106571232/8
 #define XILINX_XC7Z100_SIZE	139330784/8
 
-/* Descriptor Macros */
-#define XILINX_XC7Z007S_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z007s" }
-
-#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z010" }
-
-#define XILINX_XC7Z012S_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z012s" }
-
-#define XILINX_XC7Z014S_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z014s" }
-
-#define XILINX_XC7Z015_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z015" }
-
-#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z020" }
-
-#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z030" }
-
-#define XILINX_XC7Z035_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z035" }
-
-#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z045" }
-
-#define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z100" }
+/* Device Names */
+#define XILINX_XC7Z007S_NAME	"7z007s"
+#define XILINX_XC7Z010_NAME	"7z010"
+#define XILINX_XC7Z012S_NAME	"7z012s"
+#define XILINX_XC7Z014S_NAME	"7z014s"
+#define XILINX_XC7Z015_NAME	"7z015"
+#define XILINX_XC7Z020_NAME	"7z020"
+#define XILINX_XC7Z030_NAME	"7z030"
+#define XILINX_XC7Z035_NAME	"7z035"
+#define XILINX_XC7Z045_NAME	"7z045"
+#define XILINX_XC7Z100_NAME	"7z100"
+
+#if defined(CONFIG_FPGA)
+#define ZYNQ_DESC(name) { \
+	.idcode = XILINX_ZYNQ_XC##name, \
+	.fpga_size = XILINX_XC##name##_SIZE, \
+	.devicename = XILINX_XC##name##_NAME \
+	}
+#else
+#define ZYNQ_DESC(name) { \
+	.idcode = XILINX_ZYNQ_XC##name, \
+	.devicename = XILINX_XC##name##_NAME \
+	}
+#endif
 
 #endif /* _ZYNQPL_H_ */