diff options
| author | wdenk <wdenk> | 2004-07-09 23:27:13 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-07-09 23:27:13 +0000 |
| commit | 0ac6f8b7498d3608bd1de2280a014e9e23d7b1f2 (patch) | |
| tree | de6ad6c1ee05c1ebcee774a2e8c772e7b2e57586 /include/mpc85xx.h | |
| parent | 262381329b87511ed862cde139a3a1ff49e9d7eb (diff) | |
| download | u-boot-0ac6f8b7498d3608bd1de2280a014e9e23d7b1f2.tar.gz | |
Patch by Jon Loeliger, 17 June 2004:
Completion of the 8540ADS/8560ADS updates:
Fix some PCI and Rapid I/O memory maps,
Initialize both TSEC 1 and 2,
Initialize SDRAM
Update MAINTAINER for 85xx boards and README.mpc85xxads
Diffstat (limited to 'include/mpc85xx.h')
| -rw-r--r-- | include/mpc85xx.h | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/include/mpc85xx.h b/include/mpc85xx.h index a4f5c619d1..60b6c61fb0 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -1,4 +1,5 @@ /* + * Copyright 2004 Freescale Semiconductor. * Copyright(c) 2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) */ @@ -6,27 +7,22 @@ #ifndef __MPC85xx_H__ #define __MPC85xx_H__ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ #if defined(CONFIG_E500) #include <e500.h> #endif -#if defined(CONFIG_DDR_ECC) -void dma_init(void); -uint dma_check(void); -int dma_xfer(void *dest, uint count, void *src); -#endif -/*----------------------------------------------------------------------- - * SCCR - System Clock Control Register 9-8 +/* + * SCCR - System Clock Control Register, 9-8 */ -#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ -#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ +#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ +#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ #define SCCR_DFBRG_SHIFT 0 -#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ -#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ -#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ -#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ +#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ +#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ +#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ +#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ #endif /* __MPC85xx_H__ */ |