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authorChris Zankel <chris@zankel.net>2016-08-10 18:36:43 +0300
committerTom Rini <trini@konsulko.com>2016-08-15 18:46:38 -0400
commitde5e5cea022ab44006ff1edf45a39f0943fb9dff (patch)
tree8dbaf0260ec277035ecb514d8437bd4cd05de70e /include/image.h
parentf225d39d30935c3d27271bee676ef554fa9b0f3c (diff)
downloadu-boot-de5e5cea022ab44006ff1edf45a39f0943fb9dff.tar.gz
xtensa: add support for the xtensa processor architecture [1/2]
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence. This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/image.h')
-rw-r--r--include/image.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/image.h b/include/image.h
index 734def3117..64da722649 100644
--- a/include/image.h
+++ b/include/image.h
@@ -200,6 +200,7 @@ enum {
IH_ARCH_ARM64, /* ARM64 */
IH_ARCH_ARC, /* Synopsys DesignWare ARC */
IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */
+ IH_ARCH_XTENSA, /* Xtensa */
IH_ARCH_COUNT,
};