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| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2015-12-16 16:45:41 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-01-25 08:24:15 -0800 |
| commit | a994b3deb00bf3177cdf9f92060baec4f640f466 (patch) | |
| tree | e7e7a70b20a26ab4d63ff55ea91b867343a03b23 /include/fsl_ddr_sdram.h | |
| parent | 6f14e257c472c895499c186b602861e90f2656b5 (diff) | |
| download | u-boot-a994b3deb00bf3177cdf9f92060baec4f640f466.tar.gz | |
driver/ddr/fsl: Add workaround for A009663
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.
When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/fsl_ddr_sdram.h')
| -rw-r--r-- | include/fsl_ddr_sdram.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 9ea8b63779..3699c0408a 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -129,6 +129,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_ODT_ONLY_READ 2 #define SDRAM_CFG2_ODT_ALWAYS 3 +#define SDRAM_INTERVAL_BSTOPRE 0x3FFF #define TIMING_CFG_2_CPO_MASK 0x0F800000 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ |