diff options
| author | Stephen Warren <swarren@nvidia.com> | 2016-07-27 15:24:50 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-08-04 13:36:58 -0700 |
| commit | 7b9cb4940575f3b2d368d56ca06d3c0330af4c4b (patch) | |
| tree | a5079256405d62f1e263efcd776a003400167f41 /include/dt-bindings/power/tegra186-powergate.h | |
| parent | 729c2db7a977c59ea35bbc56fb1633c17342b3c5 (diff) | |
| download | u-boot-7b9cb4940575f3b2d368d56ca06d3c0330af4c4b.tar.gz | |
ARM: tegra: add BPMP DT bindings
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. These bindings dictate how to represent the BPMP in device tree.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/dt-bindings/power/tegra186-powergate.h')
| -rw-r--r-- | include/dt-bindings/power/tegra186-powergate.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h new file mode 100644 index 0000000000..70630c6ea7 --- /dev/null +++ b/include/dt-bindings/power/tegra186-powergate.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2015-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H +#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H + +#define TEGRA186_POWER_DOMAIN_AUD 0 +#define TEGRA186_POWER_DOMAIN_DFD 1 +#define TEGRA186_POWER_DOMAIN_DISP 2 +#define TEGRA186_POWER_DOMAIN_DISPB 3 +#define TEGRA186_POWER_DOMAIN_DISPC 4 +#define TEGRA186_POWER_DOMAIN_ISPA 5 +#define TEGRA186_POWER_DOMAIN_NVDEC 6 +#define TEGRA186_POWER_DOMAIN_NVJPG 7 +#define TEGRA186_POWER_DOMAIN_MPE 8 +#define TEGRA186_POWER_DOMAIN_PCX 9 +#define TEGRA186_POWER_DOMAIN_SAX 10 +#define TEGRA186_POWER_DOMAIN_VE 11 +#define TEGRA186_POWER_DOMAIN_VIC 12 +#define TEGRA186_POWER_DOMAIN_XUSBA 13 +#define TEGRA186_POWER_DOMAIN_XUSBB 14 +#define TEGRA186_POWER_DOMAIN_XUSBC 15 +#define TEGRA186_POWER_DOMAIN_GPU 43 +#define TEGRA186_POWER_DOMAIN_MAX 44 + +#endif |