diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2015-08-07 18:01:51 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-09-01 21:38:46 -0500 |
| commit | cf7ee6c4e37ea4bc56df4b2e543874ec68b33bc7 (patch) | |
| tree | c5a450b669bba5eba69d53ff38a6ebbe467ef008 /include/configs | |
| parent | 4c2620dd71fdba98e5a6c1e7b8326365307dae57 (diff) | |
| download | u-boot-cf7ee6c4e37ea4bc56df4b2e543874ec68b33bc7.tar.gz | |
armv8: ls2085qds: Add support of X-QSGMII-16PORT riser card
The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
interfaces implemented in PCIe form factor board.
It supports followings
- Card can operate with up to 4 QSGMII lane simultaneously
- Card can operate with up to 8 SGMII lane simultaneously
Add support of X-QSGMII-16PORT riser card.
This patch also take care of back-ward compatiblity with old SGMII rise cards
used on LS2085QDS Platform.
Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/ls2085aqds.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index f818570e55..f7f3870032 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -355,6 +355,23 @@ unsigned long get_board_ddr_clk(void); #define SGMII_CARD_PORT3_PHY_ADDR 0x1E #define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + #define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "DPNI1" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |