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| author | Michal Simek <michal.simek@xilinx.com> | 2017-11-02 10:54:48 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-11-28 16:08:47 +0100 |
| commit | dea4d2f01d3bcf5e7227a86610eec388e0186dba (patch) | |
| tree | 2f24801f673fa795a4aefb102bf19dd8dd53e0e1 /include/configs/zynq_cse.h | |
| parent | 70ca290422241ae9c9304bc34f70e7c18dfa1f29 (diff) | |
| download | u-boot-dea4d2f01d3bcf5e7227a86610eec388e0186dba.tar.gz | |
arm: zynq: Add mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configurations which runs
out of OCM.
ram top is calculated from 0 that's why +#define CONFIG_SYS_SDRAM_BASE
0xfffc0000
+#define CONFIG_SYS_SDRAM_SIZE 0x40000
was hardcoded.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/zynq_cse.h')
| -rw-r--r-- | include/configs/zynq_cse.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h new file mode 100644 index 0000000000..dd65b52343 --- /dev/null +++ b/include/configs/zynq_cse.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2013 - 2017 Xilinx. + * + * Configuration settings for the Xilinx Zynq CSE board. + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_CSE_H +#define __CONFIG_ZYNQ_CSE_H + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF + +#include <configs/zynq-common.h> + +/* Undef unneeded configs */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOARD_LATE_INIT +#undef CONFIG_BOOTCOMMAND +#undef CONFIG_ENV_SIZE +#undef CONFIG_CMDLINE_EDITING +#undef CONFIG_AUTO_COMPLETE +#undef CONFIG_ZLIB +#undef CONFIG_GZIP + +#undef CONFIG_SYS_LONGHELP + +#undef CONFIG_SYS_CBSIZE +#undef CONFIG_BOOTM_VXWORKS +#undef CONFIG_BOOTM_LINUX + +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_ENV_SIZE 400 +#undef CONFIG_SYS_INIT_RAM_ADDR +#undef CONFIG_SYS_INIT_RAM_SIZE +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#undef CONFIG_SPL_BSS_START_ADDR +#undef CONFIG_SPL_BSS_MAX_SIZE +#define CONFIG_SPL_BSS_START_ADDR 0x20000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x8000 + +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN 0x1000 + +#define CONFIG_SYS_SDRAM_BASE 0xfffc0000 +#define CONFIG_SYS_SDRAM_SIZE 0x40000 + +#endif /* __CONFIG_ZYNQ_CSE_H */ |