diff options
| author | York Sun <yorksun@freescale.com> | 2013-03-25 07:33:31 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-14 16:00:30 -0500 |
| commit | 10d644b10d35672fa8860756ce3339aac18d394f (patch) | |
| tree | ba1dd359f4bde5f0d2336484b9ba3bd4ea55ed72 /include/configs/t4qds.h | |
| parent | b46b7f9898bd6d4de0e5539b00dea3d740096702 (diff) | |
| download | u-boot-10d644b10d35672fa8860756ce3339aac18d394f.tar.gz | |
powerpc: Add T4160QDS
T4160QDS shares the same platform as T4240QDS. T4160 is a low power
version of T4240, with eight e6500 cores, two DDR3 controllers, and
slightly different SerDes protocols.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs/t4qds.h')
| -rw-r--r-- | include/configs/t4qds.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index dbaa7ea9d3..a8346f0800 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -791,8 +791,21 @@ unsigned long get_board_ddr_clk(void); #define __USB_PHY_TYPE utmi +/* + * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be + * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to + * cacheline interleaving. It can be cacheline, page, bank, superbank. + * See doc/README.fsl-ddr for details. + */ +#ifdef CONFIG_PPC_T4240 +#define CTRL_INTLV_PREFERED 3way_4KB +#else +#define CTRL_INTLV_PREFERED cacheline +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ "bank_intlv=auto;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ |