diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-10-10 16:21:15 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-11-21 23:57:22 +0100 |
| commit | 4d9253fb76f59c6f474ca54fe2d45c5706cd86e3 (patch) | |
| tree | ae013dd63968e48a8650479fcdb35808b50949fb /include/configs/rk3188_common.h | |
| parent | ecfd71891a81b2db0aada07306e8bc54b4273179 (diff) | |
| download | u-boot-4d9253fb76f59c6f474ca54fe2d45c5706cd86e3.tar.gz | |
rockchip: rk3188: use boot0 hook to load up SPL in 2 steps
For the RK3188, the BROM will attempt to load up the first stage
image (SPL for the RK3188) in two steps: first 1KB to offset 0x800
in the SRAM and then the remainder to offset 0xc00 in the SRAM.
It always enters at 0x804, though.
With this changeset, the RK3188 boot removes the TPL (stub) stage and
builds a single SPL binary that utilizes the early back-to-bootrom via
the boot0-hook.
Consequently, the passing of the saved boot params via pmu->os_reg[2]
is also removed.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'include/configs/rk3188_common.h')
| -rw-r--r-- | include/configs/rk3188_common.h | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index cfa5364710..68a42a95d9 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -36,14 +36,9 @@ #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_TEXT_BASE 0x10080804 -/* tpl size 1kb - 4byte RK31 header */ -#define CONFIG_SPL_MAX_SIZE (0x400 - 0x4) -#elif defined(CONFIG_SPL_BUILD) -/* spl size 32kb sram - 2kb bootrom - 1kb spl */ -#define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00) -#define CONFIG_SPL_TEXT_BASE 0x10080C00 +#define CONFIG_SPL_TEXT_BASE 0x10080800 +/* spl size 32kb sram - 2kb bootrom */ +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800) #define CONFIG_SPL_FRAMEWORK 1 #define CONFIG_SPL_CLK 1 #define CONFIG_SPL_PINCTRL 1 @@ -52,7 +47,6 @@ #define CONFIG_SPL_RAM 1 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1 #define CONFIG_ROCKCHIP_SERIAL 1 -#endif #define CONFIG_SPL_STACK 0x10087fff |