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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-08-13 00:29:15 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-08-26 07:54:08 -0700 |
| commit | 3ff2f001c2289186c88edf55779078395987bb60 (patch) | |
| tree | 8a82e7ff82387ff7f76c29ab381d4d14dcb646da /include/configs/crownbay.h | |
| parent | c80ff560347820c5472bbd39e5b709df325cc6c8 (diff) | |
| download | u-boot-3ff2f001c2289186c88edf55779078395987bb60.tar.gz | |
x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'include/configs/crownbay.h')
| -rw-r--r-- | include/configs/crownbay.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 57a9512f07..162f08ff1e 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -31,7 +31,6 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xe000 -#define CONFIG_PCI_CONFIG_HOST_BRIDGE #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP |