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| author | York Sun <yorksun@freescale.com> | 2012-02-29 12:36:51 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-04-24 23:58:30 -0500 |
| commit | 1ba62f10172ead798a8176435cfffff2f79f21c5 (patch) | |
| tree | 5e9b575825060fae4ebefa3193ad5f1124c0fefd /include/configs/P1010RDB.h | |
| parent | 119a55f9cff4884a0ad3353d8752ee8787e232da (diff) | |
| download | u-boot-1ba62f10172ead798a8176435cfffff2f79f21c5.tar.gz | |
powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs/P1010RDB.h')
| -rw-r--r-- | include/configs/P1010RDB.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f2d33668d8..08fc4e8427 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -181,7 +181,7 @@ /* DDR Setup */ #define CONFIG_FSL_DDR3 -#define CONFIG_DDR_RAW_TIMING +#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 |