diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-05-24 12:56:53 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-05-24 12:56:53 +0200 |
| commit | 42fd5f87b1613d3039f57e93c16f760a768d3e84 (patch) | |
| tree | 9dd0252fca37dbdb1148ce7fd44dc5c9dd8a6b34 /include/asm-arm/arch-at91sam9/at91cap9.h | |
| parent | 2c8d41969b47eb0b973912830c58689b2ba0e50a (diff) | |
| parent | 54694a91428f6c3280fe1ee0923488a1e7e8dbc4 (diff) | |
| download | u-boot-42fd5f87b1613d3039f57e93c16f760a768d3e84.tar.gz | |
Merging Stelian Pop AT91 patches
Merge branch 'testing-V2'
Conflicts:
board/atmel/at91cap9adk/Makefile
Fixing copyright
board/atmel/at91sam9260ek/Makefile
Fixing copyright
board/atmel/at91sam9260ek/u-boot.lds
Delete no more needed ld script
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'include/asm-arm/arch-at91sam9/at91cap9.h')
| -rw-r--r-- | include/asm-arm/arch-at91sam9/at91cap9.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/include/asm-arm/arch-at91sam9/at91cap9.h b/include/asm-arm/arch-at91sam9/at91cap9.h index d1b33a069a..0b52228138 100644 --- a/include/asm-arm/arch-at91sam9/at91cap9.h +++ b/include/asm-arm/arch-at91sam9/at91cap9.h @@ -101,13 +101,25 @@ #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS) #define AT91_USART0 AT91CAP9_BASE_US0 #define AT91_USART1 AT91CAP9_BASE_US1 #define AT91_USART2 AT91CAP9_BASE_US2 /* + * SCKCR flags + */ +#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ +#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ +#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ +#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ +#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3) +#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3) + +/* * Internal Memory. */ #define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ |