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| author | Tom Rini <trini@konsulko.com> | 2022-09-18 11:41:08 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-09-18 11:41:08 -0400 |
| commit | 0b3fe2b9777eff12ffd6735fc00291616b407622 (patch) | |
| tree | 03fce69a0e56be3e2838c0528f31cd9eb0be57a2 /drivers | |
| parent | 1977d72a69f3c8d97bd25a86a6be4da27cde3724 (diff) | |
| parent | 5a428e751044525f95d15f180188cc7433648b82 (diff) | |
| download | u-boot-0b3fe2b9777eff12ffd6735fc00291616b407622.tar.gz | |
Merge branch 'mpc85xx-for-v2022.10-rc5' of https://source.denx.de/u-boot/custodians/u-boot-mpc85xx
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/fsl_esdhc_spl.c | 43 |
1 files changed, 34 insertions, 9 deletions
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 760f13d240..aa00d7e201 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -9,6 +9,10 @@ #include <mmc.h> #include <malloc.h> +#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS +extern uchar mmc_u_boot_offs[]; +#endif + /* * The environment variables are written to just after the u-boot image * on SDCard, so we must read the MBR to get the start address and code @@ -58,10 +62,10 @@ void __noreturn mmc_boot(void) { __attribute__((noreturn)) void (*uboot)(void); uint blk_start, blk_cnt, err; -#ifndef CONFIG_FSL_CORENET uchar *tmp_buf; u32 blklen; u32 blk_off; +#ifndef CONFIG_FSL_CORENET uchar val; #ifndef CONFIG_SPL_FSL_PBL u32 val32; @@ -83,9 +87,6 @@ void __noreturn mmc_boot(void) hang(); } -#ifdef CONFIG_FSL_CORENET - offset = CONFIG_SYS_MMC_U_BOOT_OFFS; -#else blklen = mmc->read_bl_len; if (blklen < 512) blklen = 512; @@ -95,6 +96,9 @@ void __noreturn mmc_boot(void) hang(); } +#ifdef CONFIG_FSL_CORENET + offset = CONFIG_SYS_MMC_U_BOOT_OFFS; +#else sector = 0; again: memset(tmp_buf, 0, blklen); @@ -149,23 +153,44 @@ again: val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i); offset = (offset << 8) + val; } +#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS + offset += (ulong)&mmc_u_boot_offs - CONFIG_SPL_TEXT_BASE; +#else offset += CONFIG_SYS_MMC_U_BOOT_OFFS; #endif +#endif /* * Load U-Boot image from mmc into RAM */ code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; - blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; - blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; + blk_start = offset / mmc->read_bl_len; + blk_off = offset % mmc->read_bl_len; + blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1; + if (blk_off) { + err = mmc->block_dev.block_read(&mmc->block_dev, + blk_start, 1, tmp_buf); + if (err != 1) { + puts("spl: mmc read failed!!\n"); + hang(); + } + blk_start++; + } err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, - (uchar *)CONFIG_SYS_MMC_U_BOOT_DST); + (uchar *)CONFIG_SYS_MMC_U_BOOT_DST + + (blk_off ? (mmc->read_bl_len - blk_off) : 0)); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); -#ifndef CONFIG_FSL_CORENET free(tmp_buf); -#endif hang(); } + /* + * SDHC DMA may erase bytes at dst + bl_len - blk_off - 8 + * due to unaligned access. So copy leading bytes from tmp_buf + * after SDHC DMA transfer. + */ + if (blk_off) + memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST, + tmp_buf + blk_off, mmc->read_bl_len - blk_off); /* * Clean d-cache and invalidate i-cache, to |