Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchip

Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie

17 files changed, 938 insertions, 413 deletions

diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index 48ed14b2af..f09730c91b 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -121,10 +121,10 @@ static void rkclk_init(struct rk322x_cru *cru)
 	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 
 	pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
-	assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
+	assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
 
 	hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
-	assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
+	assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
 
 	rk_clrsetreg(&cru->cru_clksel_con[0],
 		     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
@@ -217,6 +217,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
 	switch (periph) {
 	case HCLK_EMMC:
 	case SCLK_EMMC:
+	case SCLK_EMMC_SAMPLE:
 		con = readl(&cru->cru_clksel_con[11]);
 		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
 		con = readl(&cru->cru_clksel_con[12]);
@@ -293,6 +294,7 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
 	switch (periph) {
 	case HCLK_EMMC:
 	case SCLK_EMMC:
+	case SCLK_EMMC_SAMPLE:
 		rk_clrsetreg(&cru->cru_clksel_con[11],
 			     EMMC_PLL_MASK,
 			     mux << EMMC_PLL_SHIFT);
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
index 2729b03443..28c905129b 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
@@ -11,6 +11,30 @@
 
 #include "pinctrl-rockchip.h"
 
+static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data;
+
+	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+				? priv->regmap_pmu : priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3036_PULL_OFFSET		0x118
 #define RK3036_PULL_PINS_PER_REG	16
 #define RK3036_PULL_BANK_STRIDE		8
@@ -29,6 +53,27 @@ static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 	*bit = pin_num % RK3036_PULL_PINS_PER_REG;
 };
 
+static int rk3036_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit;
+	u32 data;
+
+	if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
+	    pull != PIN_CONFIG_BIAS_DISABLE)
+		return -ENOTSUPP;
+
+	rk3036_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	data = BIT(bit + 16);
+	if (pull == PIN_CONFIG_BIAS_DISABLE)
+		data |= BIT(bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 static struct rockchip_pin_bank rk3036_pin_banks[] = {
 	PIN_BANK(0, 32, "gpio0"),
 	PIN_BANK(1, 32, "gpio1"),
@@ -36,12 +81,11 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
 };
 
 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
-		.pin_banks		= rk3036_pin_banks,
-		.nr_banks		= ARRAY_SIZE(rk3036_pin_banks),
-		.label			= "RK3036-GPIO",
-		.type			= RK3036,
-		.grf_mux_offset		= 0xa8,
-		.pull_calc_reg		= rk3036_calc_pull_reg_and_bit,
+	.pin_banks		= rk3036_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3036_pin_banks),
+	.grf_mux_offset		= 0xa8,
+	.set_mux		= rk3036_set_mux,
+	.set_pull		= rk3036_set_pull,
 };
 
 static const struct udevice_id rk3036_pinctrl_ids[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
index 43a6c173a0..3eb4d952bb 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
@@ -98,6 +98,42 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 	},
 };
 
+static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data, route_reg, route_val;
+
+	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+				? priv->regmap_pmu : priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	if (bank->recalced_mask & BIT(pin))
+		rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
+
+	if (bank->route_mask & BIT(pin)) {
+		if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+					   &route_val)) {
+			ret = regmap_write(regmap, route_reg, route_val);
+			if (ret)
+				return ret;
+		}
+	}
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3128_PULL_OFFSET		0x118
 #define RK3128_PULL_PINS_PER_REG	16
 #define RK3128_PULL_BANK_STRIDE		8
@@ -116,6 +152,27 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 	*bit = pin_num % RK3128_PULL_PINS_PER_REG;
 }
 
+static int rk3128_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit;
+	u32 data;
+
+	if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
+	    pull != PIN_CONFIG_BIAS_DISABLE)
+		return -ENOTSUPP;
+
+	rk3128_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	data = BIT(bit + 16);
+	if (pull == PIN_CONFIG_BIAS_DISABLE)
+		data |= BIT(bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 static struct rockchip_pin_bank rk3128_pin_banks[] = {
 	PIN_BANK(0, 32, "gpio0"),
 	PIN_BANK(1, 32, "gpio1"),
@@ -126,14 +183,13 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
 	.pin_banks		= rk3128_pin_banks,
 	.nr_banks		= ARRAY_SIZE(rk3128_pin_banks),
-	.label			= "RK3128-GPIO",
-	.type			= RK3128,
 	.grf_mux_offset		= 0xa8,
 	.iomux_recalced		= rk3128_mux_recalced_data,
 	.niomux_recalced	= ARRAY_SIZE(rk3128_mux_recalced_data),
 	.iomux_routes		= rk3128_mux_route_data,
 	.niomux_routes		= ARRAY_SIZE(rk3128_mux_route_data),
-	.pull_calc_reg		= rk3128_calc_pull_reg_and_bit,
+	.set_mux		= rk3128_set_mux,
+	.set_pull		= rk3128_set_pull,
 };
 
 static const struct udevice_id rk3128_pinctrl_ids[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c
index 5ed9aec938..043764fc92 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c
@@ -11,6 +11,30 @@
 
 #include "pinctrl-rockchip.h"
 
+static int rk3188_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data;
+
+	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+				? priv->regmap_pmu : priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3188_PULL_OFFSET		0x164
 #define RK3188_PULL_PMU_OFFSET		0x64
 
@@ -47,6 +71,33 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 	}
 }
 
+static int rk3188_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
+
+	rk3188_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 static struct rockchip_pin_bank rk3188_pin_banks[] = {
 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
 	PIN_BANK(1, 32, "gpio1"),
@@ -55,12 +106,11 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = {
 };
 
 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
-		.pin_banks		= rk3188_pin_banks,
-		.nr_banks		= ARRAY_SIZE(rk3188_pin_banks),
-		.label			= "RK3188-GPIO",
-		.type			= RK3188,
-		.grf_mux_offset		= 0x60,
-		.pull_calc_reg		= rk3188_calc_pull_reg_and_bit,
+	.pin_banks		= rk3188_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3188_pin_banks),
+	.grf_mux_offset		= 0x60,
+	.set_mux		= rk3188_set_mux,
+	.set_pull		= rk3188_set_pull,
 };
 
 static const struct udevice_id rk3188_pinctrl_ids[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
index d2a6cd7055..c5e4fe30a7 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
@@ -141,6 +141,39 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 	},
 };
 
+static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data, route_reg, route_val;
+
+	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+				? priv->regmap_pmu : priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	if (bank->route_mask & BIT(pin)) {
+		if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+					   &route_val)) {
+			ret = regmap_write(regmap, route_reg, route_val);
+			if (ret)
+				return ret;
+		}
+	}
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3228_PULL_OFFSET		0x100
 
 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
@@ -158,6 +191,33 @@ static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 	*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
 }
 
+static int rk3228_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
+
+	rk3228_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3228_DRV_GRF_OFFSET		0x200
 
 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
@@ -175,6 +235,29 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 }
 
+static int rk3228_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data;
+	u8 bit;
+	int type = bank->drv[pin_num / 8].drv_type;
+
+	rk3228_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ret = rockchip_translate_drive_value(type, strength);
+	if (ret < 0) {
+		debug("unsupported driver strength %d\n", strength);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+	return ret;
+}
+
 static struct rockchip_pin_bank rk3228_pin_banks[] = {
 	PIN_BANK(0, 32, "gpio0"),
 	PIN_BANK(1, 32, "gpio1"),
@@ -183,15 +266,14 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = {
 };
 
 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
-		.pin_banks		= rk3228_pin_banks,
-		.nr_banks		= ARRAY_SIZE(rk3228_pin_banks),
-		.label			= "RK3228-GPIO",
-		.type			= RK3288,
-		.grf_mux_offset		= 0x0,
-		.iomux_routes		= rk3228_mux_route_data,
-		.niomux_routes		= ARRAY_SIZE(rk3228_mux_route_data),
-		.pull_calc_reg		= rk3228_calc_pull_reg_and_bit,
-		.drv_calc_reg		= rk3228_calc_drv_reg_and_bit,
+	.pin_banks		= rk3228_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3228_pin_banks),
+	.grf_mux_offset		= 0x0,
+	.iomux_routes		= rk3228_mux_route_data,
+	.niomux_routes		= ARRAY_SIZE(rk3228_mux_route_data),
+	.set_mux		= rk3228_set_mux,
+	.set_pull		= rk3228_set_pull,
+	.set_drive		= rk3228_set_drive,
 };
 
 static const struct udevice_id rk3228_pinctrl_ids[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
index 8b6ce11a63..7ae147f304 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
@@ -7,7 +7,6 @@
 #include <dm.h>
 #include <dm/pinctrl.h>
 #include <regmap.h>
-#include <syscon.h>
 
 #include "pinctrl-rockchip.h"
 
@@ -29,6 +28,47 @@ static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 	},
 };
 
+static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data, route_reg, route_val;
+
+	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+				? priv->regmap_pmu : priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	if (bank->route_mask & BIT(pin)) {
+		if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+					   &route_val)) {
+			ret = regmap_write(regmap, route_reg, route_val);
+			if (ret)
+				return ret;
+		}
+	}
+
+	/* bank0 is special, there are no higher 16 bit writing bits. */
+	if (bank->bank_num == 0) {
+		regmap_read(regmap, reg, &data);
+		data &= ~(mask << bit);
+	} else {
+		/* enable the write to the equivalent lower bits */
+		data = (mask << (bit + 16));
+	}
+
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3288_PULL_OFFSET		0x140
 #define RK3288_PULL_PMU_OFFSET          0x64
 
@@ -42,10 +82,6 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 	if (bank->bank_num == 0) {
 		*regmap = priv->regmap_pmu;
 		*reg = RK3288_PULL_PMU_OFFSET;
-
-		*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
-		*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
-		*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
 	} else {
 		*regmap = priv->regmap_base;
 		*reg = RK3288_PULL_OFFSET;
@@ -53,11 +89,46 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 		/* correct the offset, as we're starting with the 2nd bank */
 		*reg -= 0x10;
 		*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
-		*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+	}
+
+	*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+
+	*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
+	*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+}
+
+static int rk3288_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
+
+	rk3288_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
 
-		*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
-		*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+	/* bank0 is special, there are no higher 16 bit writing bits */
+	if (bank->bank_num == 0) {
+		regmap_read(regmap, reg, &data);
+		data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
+	} else {
+		/* enable the write to the equivalent lower bits */
+		data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 	}
+
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
 }
 
 #define RK3288_DRV_PMU_OFFSET		0x70
@@ -73,10 +144,6 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 	if (bank->bank_num == 0) {
 		*regmap = priv->regmap_pmu;
 		*reg = RK3288_DRV_PMU_OFFSET;
-
-		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
-		*bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
-		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 	} else {
 		*regmap = priv->regmap_base;
 		*reg = RK3288_DRV_GRF_OFFSET;
@@ -84,27 +151,48 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 		/* correct the offset, as we're starting with the 2nd bank */
 		*reg -= 0x10;
 		*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
-		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+	}
 
-		*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
-		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+	*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+	*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
+	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+}
+
+static int rk3288_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data;
+	u8 bit;
+	int type = bank->drv[pin_num / 8].drv_type;
+
+	rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ret = rockchip_translate_drive_value(type, strength);
+	if (ret < 0) {
+		debug("unsupported driver strength %d\n", strength);
+		return ret;
+	}
+
+	/* bank0 is special, there are no higher 16 bit writing bits. */
+	if (bank->bank_num == 0) {
+		regmap_read(regmap, reg, &data);
+		data &= ~(((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << bit);
+	} else {
+		/* enable the write to the equivalent lower bits */
+		data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 	}
+
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+	return ret;
 }
 
 static struct rockchip_pin_bank rk3288_pin_banks[] = {
-	PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
-				      IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
-				      IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
-				      IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
-				      IOMUX_UNROUTED,
-				      DRV_TYPE_WRITABLE_32BIT,
-				      DRV_TYPE_WRITABLE_32BIT,
-				      DRV_TYPE_WRITABLE_32BIT,
-				      0,
-				      PULL_TYPE_WRITABLE_32BIT,
-				      PULL_TYPE_WRITABLE_32BIT,
-				      PULL_TYPE_WRITABLE_32BIT,
-				      0
+	PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
+					     IOMUX_SOURCE_PMU,
+					     IOMUX_SOURCE_PMU,
+					     IOMUX_UNROUTED
 			    ),
 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
 					     IOMUX_UNROUTED,
@@ -133,16 +221,15 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = {
 };
 
 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
-		.pin_banks		= rk3288_pin_banks,
-		.nr_banks		= ARRAY_SIZE(rk3288_pin_banks),
-		.label			= "RK3288-GPIO",
-		.type			= RK3288,
-		.grf_mux_offset		= 0x0,
-		.pmu_mux_offset		= 0x84,
-		.iomux_routes		= rk3288_mux_route_data,
-		.niomux_routes		= ARRAY_SIZE(rk3288_mux_route_data),
-		.pull_calc_reg		= rk3288_calc_pull_reg_and_bit,
-		.drv_calc_reg		= rk3288_calc_drv_reg_and_bit,
+	.pin_banks		= rk3288_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3288_pin_banks),
+	.grf_mux_offset		= 0x0,
+	.pmu_mux_offset		= 0x84,
+	.iomux_routes		= rk3288_mux_route_data,
+	.niomux_routes		= ARRAY_SIZE(rk3288_mux_route_data),
+	.set_mux		= rk3288_set_mux,
+	.set_pull		= rk3288_set_pull,
+	.set_drive		= rk3288_set_drive,
 };
 
 static const struct udevice_id rk3288_pinctrl_ids[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
index f1b3d10dbe..8d37a6f945 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
@@ -121,6 +121,42 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 	},
 };
 
+static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data, route_reg, route_val;
+
+	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+				? priv->regmap_pmu : priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	if (bank->recalced_mask & BIT(pin))
+		rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
+
+	if (bank->route_mask & BIT(pin)) {
+		if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+					   &route_val)) {
+			ret = regmap_write(regmap, route_reg, route_val);
+			if (ret)
+				return ret;
+		}
+	}
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3328_PULL_OFFSET		0x100
 
 static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
@@ -138,6 +174,33 @@ static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 	*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
 }
 
+static int rk3328_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
+
+	rk3328_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3328_DRV_GRF_OFFSET		0x200
 
 static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
@@ -155,6 +218,30 @@ static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 }
 
+static int rk3328_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data;
+	u8 bit;
+	int type = bank->drv[pin_num / 8].drv_type;
+
+	rk3328_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ret = rockchip_translate_drive_value(type, strength);
+	if (ret < 0) {
+		debug("unsupported driver strength %d\n", strength);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3328_SCHMITT_BITS_PER_PIN		1
 #define RK3328_SCHMITT_PINS_PER_REG		16
 #define RK3328_SCHMITT_BANK_STRIDE		8
@@ -177,6 +264,21 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
 	return 0;
 }
 
+static int rk3328_set_schmitt(struct rockchip_pin_bank *bank,
+			      int pin_num, int enable)
+{
+	struct regmap *regmap;
+	int reg;
+	u8 bit;
+	u32 data;
+
+	rk3328_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	/* enable the write to the equivalent lower bits */
+	data = BIT(bit + 16) | (enable << bit);
+
+	return regmap_write(regmap, reg, data);
+}
+
 static struct rockchip_pin_bank rk3328_pin_banks[] = {
 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
@@ -192,18 +294,17 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
 };
 
 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
-		.pin_banks		= rk3328_pin_banks,
-		.nr_banks		= ARRAY_SIZE(rk3328_pin_banks),
-		.label			= "RK3328-GPIO",
-		.type			= RK3288,
-		.grf_mux_offset		= 0x0,
-		.iomux_recalced		= rk3328_mux_recalced_data,
-		.niomux_recalced	= ARRAY_SIZE(rk3328_mux_recalced_data),
-		.iomux_routes		= rk3328_mux_route_data,
-		.niomux_routes		= ARRAY_SIZE(rk3328_mux_route_data),
-		.pull_calc_reg		= rk3328_calc_pull_reg_and_bit,
-		.drv_calc_reg		= rk3328_calc_drv_reg_and_bit,
-		.schmitt_calc_reg	= rk3328_calc_schmitt_reg_and_bit,
+	.pin_banks		= rk3328_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3328_pin_banks),
+	.grf_mux_offset		= 0x0,
+	.iomux_recalced		= rk3328_mux_recalced_data,
+	.niomux_recalced	= ARRAY_SIZE(rk3328_mux_recalced_data),
+	.iomux_routes		= rk3328_mux_route_data,
+	.niomux_routes		= ARRAY_SIZE(rk3328_mux_route_data),
+	.set_mux		= rk3328_set_mux,
+	.set_pull		= rk3328_set_pull,
+	.set_drive		= rk3328_set_drive,
+	.set_schmitt		= rk3328_set_schmitt,
 };
 
 static const struct udevice_id rk3328_pinctrl_ids[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
index f5cd6ff24e..6cb7bb45d9 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
@@ -11,6 +11,30 @@
 
 #include "pinctrl-rockchip.h"
 
+static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data;
+
+	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+				? priv->regmap_pmu : priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3368_PULL_GRF_OFFSET		0x100
 #define RK3368_PULL_PMU_OFFSET		0x10
 
@@ -24,10 +48,6 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 	if (bank->bank_num == 0) {
 		*regmap = priv->regmap_pmu;
 		*reg = RK3368_PULL_PMU_OFFSET;
-
-		*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
-		*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
-		*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
 	} else {
 		*regmap = priv->regmap_base;
 		*reg = RK3368_PULL_GRF_OFFSET;
@@ -35,11 +55,39 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 		/* correct the offset, as we're starting with the 2nd bank */
 		*reg -= 0x10;
 		*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
-		*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+	}
+
+	*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
 
-		*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
-		*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+	*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
+	*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+}
+
+static int rk3368_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
+
+	rk3368_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
 	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
 }
 
 #define RK3368_DRV_PMU_OFFSET		0x20
@@ -55,10 +103,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 	if (bank->bank_num == 0) {
 		*regmap = priv->regmap_pmu;
 		*reg = RK3368_DRV_PMU_OFFSET;
-
-		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
-		*bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
-		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 	} else {
 		*regmap = priv->regmap_base;
 		*reg = RK3368_DRV_GRF_OFFSET;
@@ -66,11 +110,35 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 		/* correct the offset, as we're starting with the 2nd bank */
 		*reg -= 0x10;
 		*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
-		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+	}
 
-		*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
-		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+	*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+	*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
+	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+}
+
+static int rk3368_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data;
+	u8 bit;
+	int type = bank->drv[pin_num / 8].drv_type;
+
+	rk3368_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ret = rockchip_translate_drive_value(type, strength);
+	if (ret < 0) {
+		debug("unsupported driver strength %d\n", strength);
+		return ret;
 	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
 }
 
 static struct rockchip_pin_bank rk3368_pin_banks[] = {
@@ -85,14 +153,13 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = {
 };
 
 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
-		.pin_banks		= rk3368_pin_banks,
-		.nr_banks		= ARRAY_SIZE(rk3368_pin_banks),
-		.label			= "RK3368-GPIO",
-		.type			= RK3368,
-		.grf_mux_offset		= 0x0,
-		.pmu_mux_offset		= 0x0,
-		.pull_calc_reg		= rk3368_calc_pull_reg_and_bit,
-		.drv_calc_reg		= rk3368_calc_drv_reg_and_bit,
+	.pin_banks		= rk3368_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3368_pin_banks),
+	.grf_mux_offset		= 0x0,
+	.pmu_mux_offset		= 0x0,
+	.set_mux		= rk3368_set_mux,
+	.set_pull		= rk3368_set_pull,
+	.set_drive		= rk3368_set_drive,
 };
 
 static const struct udevice_id rk3368_pinctrl_ids[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c
index c5aab647a5..75634e9f4d 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c
@@ -50,6 +50,39 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
 	},
 };
 
+static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data, route_reg, route_val;
+
+	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+				? priv->regmap_pmu : priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	if (bank->route_mask & BIT(pin)) {
+		if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+					   &route_val)) {
+			ret = regmap_write(regmap, route_reg, route_val);
+			if (ret)
+				return ret;
+		}
+	}
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3399_PULL_GRF_OFFSET		0xe040
 #define RK3399_PULL_PMU_OFFSET		0x40
 
@@ -65,10 +98,6 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 		*reg = RK3399_PULL_PMU_OFFSET;
 
 		*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
-
-		*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
-		*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
-		*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
 	} else {
 		*regmap = priv->regmap_base;
 		*reg = RK3399_PULL_GRF_OFFSET;
@@ -76,11 +105,39 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 		/* correct the offset, as we're starting with the 3rd bank */
 		*reg -= 0x20;
 		*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
-		*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+	}
+
+	*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+
+	*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
+	*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+}
+
+static int rk3399_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
 
-		*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
-		*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+	rk3399_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
 	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
 }
 
 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
@@ -104,6 +161,79 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 		*bit = (pin_num % 8) * 2;
 }
 
+static int rk3399_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data, rmask_bits, temp;
+	u8 bit;
+	int drv_type = bank->drv[pin_num / 8].drv_type;
+
+	rk3399_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ret = rockchip_translate_drive_value(drv_type, strength);
+	if (ret < 0) {
+		debug("unsupported driver strength %d\n", strength);
+		return ret;
+	}
+
+	switch (drv_type) {
+	case DRV_TYPE_IO_1V8_3V0_AUTO:
+	case DRV_TYPE_IO_3V3_ONLY:
+		rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
+		switch (bit) {
+		case 0 ... 12:
+			/* regular case, nothing to do */
+			break;
+		case 15:
+			/*
+			 * drive-strength offset is special, as it is spread
+			 * over 2 registers, the bit data[15] contains bit 0
+			 * of the value while temp[1:0] contains bits 2 and 1
+			 */
+			data = (ret & 0x1) << 15;
+			temp = (ret >> 0x1) & 0x3;
+
+			data |= BIT(31);
+			ret = regmap_write(regmap, reg, data);
+			if (ret)
+				return ret;
+
+			temp |= (0x3 << 16);
+			reg += 0x4;
+			ret = regmap_write(regmap, reg, temp);
+
+			return ret;
+		case 18 ... 21:
+			/* setting fully enclosed in the second register */
+			reg += 4;
+			bit -= 16;
+			break;
+		default:
+			debug("unsupported bit: %d for pinctrl drive type: %d\n",
+			      bit, drv_type);
+			return -EINVAL;
+		}
+		break;
+	case DRV_TYPE_IO_DEFAULT:
+	case DRV_TYPE_IO_1V8_OR_3V0:
+	case DRV_TYPE_IO_1V8_ONLY:
+		rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
+		break;
+	default:
+		debug("unsupported pinctrl drive type: %d\n",
+		      drv_type);
+		return -EINVAL;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << rmask_bits) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 static struct rockchip_pin_bank rk3399_pin_banks[] = {
 	PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
 							 IOMUX_SOURCE_PMU,
@@ -158,18 +288,17 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
 };
 
 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
-		.pin_banks		= rk3399_pin_banks,
-		.nr_banks		= ARRAY_SIZE(rk3399_pin_banks),
-		.label			= "RK3399-GPIO",
-		.type			= RK3399,
-		.grf_mux_offset		= 0xe000,
-		.pmu_mux_offset		= 0x0,
-		.grf_drv_offset		= 0xe100,
-		.pmu_drv_offset		= 0x80,
-		.iomux_routes		= rk3399_mux_route_data,
-		.niomux_routes		= ARRAY_SIZE(rk3399_mux_route_data),
-		.pull_calc_reg		= rk3399_calc_pull_reg_and_bit,
-		.drv_calc_reg		= rk3399_calc_drv_reg_and_bit,
+	.pin_banks		= rk3399_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3399_pin_banks),
+	.grf_mux_offset		= 0xe000,
+	.pmu_mux_offset		= 0x0,
+	.grf_drv_offset		= 0xe100,
+	.pmu_drv_offset		= 0x80,
+	.iomux_routes		= rk3399_mux_route_data,
+	.niomux_routes		= ARRAY_SIZE(rk3399_mux_route_data),
+	.set_mux		= rk3399_set_mux,
+	.set_pull		= rk3399_set_pull,
+	.set_drive		= rk3399_set_drive,
 };
 
 static const struct udevice_id rk3399_pinctrl_ids[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index ce935656f0..80dc431d20 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -35,8 +35,8 @@ static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
 	return 0;
 }
 
-static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
-				      int *reg, u8 *bit, int *mask)
+void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
+			       int *reg, u8 *bit, int *mask)
 {
 	struct rockchip_pinctrl_priv *priv = bank->priv;
 	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
@@ -58,8 +58,8 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 	*bit = data->bit;
 }
 
-static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
-				   int mux, u32 *reg, u32 *value)
+bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
+			    int mux, u32 *reg, u32 *value)
 {
 	struct rockchip_pinctrl_priv *priv = bank->priv;
 	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
@@ -82,7 +82,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
 	return true;
 }
 
-static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
+int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
 {
 	int offset = 0;
 
@@ -193,11 +193,9 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 {
 	struct rockchip_pinctrl_priv *priv = bank->priv;
+	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 	int iomux_num = (pin / 8);
-	struct regmap *regmap;
-	int reg, ret, mask, mux_type;
-	u8 bit;
-	u32 data, route_reg, route_val;
+	int ret;
 
 	ret = rockchip_verify_mux(bank, pin, mux);
 	if (ret < 0)
@@ -208,35 +206,10 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 
 	debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
 
-	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
-				? priv->regmap_pmu : priv->regmap_base;
+	if (!ctrl->set_mux)
+		return -ENOTSUPP;
 
-	/* get basic quadrupel of mux registers and the correct reg inside */
-	mux_type = bank->iomux[iomux_num].type;
-	reg = bank->iomux[iomux_num].offset;
-	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
-
-	if (bank->recalced_mask & BIT(pin))
-		rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
-
-	if (bank->route_mask & BIT(pin)) {
-		if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
-					   &route_val)) {
-			ret = regmap_write(regmap, route_reg, route_val);
-			if (ret)
-				return ret;
-		}
-	}
-
-	if (mux_type & IOMUX_WRITABLE_32BIT) {
-		regmap_read(regmap, reg, &data);
-		data &= ~(mask << bit);
-	} else {
-		data = (mask << (bit + 16));
-	}
-
-	data |= (mux & mask) << bit;
-	ret = regmap_write(regmap, reg, data);
+	ret = ctrl->set_mux(bank, pin, mux);
 
 	return ret;
 }
@@ -249,99 +222,37 @@ static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
 	{ 4, 7, 10, 13, 16, 19, 22, 26 }
 };
 
-static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
-				     int pin_num, int strength)
+int rockchip_translate_drive_value(int type, int strength)
 {
-	struct rockchip_pinctrl_priv *priv = bank->priv;
-	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
-	struct regmap *regmap;
-	int reg, ret, i;
-	u32 data, rmask_bits, temp;
-	u8 bit;
-	/* Where need to clean the special mask for rockchip_perpin_drv_list */
-	int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK);
-
-	debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
-	      pin_num, strength);
-
-	ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
+	int i, ret;
 
 	ret = -EINVAL;
-	for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
-		if (rockchip_perpin_drv_list[drv_type][i] == strength) {
+	for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
+		if (rockchip_perpin_drv_list[type][i] == strength) {
 			ret = i;
 			break;
-		} else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
-			ret = rockchip_perpin_drv_list[drv_type][i];
+		} else if (rockchip_perpin_drv_list[type][i] < 0) {
+			ret = rockchip_perpin_drv_list[type][i];
 			break;
 		}
 	}
 
-	if (ret < 0) {
-		debug("unsupported driver strength %d\n", strength);
-		return ret;
-	}
-
-	switch (drv_type) {
-	case DRV_TYPE_IO_1V8_3V0_AUTO:
-	case DRV_TYPE_IO_3V3_ONLY:
-		rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
-		switch (bit) {
-		case 0 ... 12:
-			/* regular case, nothing to do */
-			break;
-		case 15:
-			/*
-			 * drive-strength offset is special, as it is spread
-			 * over 2 registers, the bit data[15] contains bit 0
-			 * of the value while temp[1:0] contains bits 2 and 1
-			 */
-			data = (ret & 0x1) << 15;
-			temp = (ret >> 0x1) & 0x3;
-
-			data |= BIT(31);
-			ret = regmap_write(regmap, reg, data);
-			if (ret)
-				return ret;
+	return ret;
+}
 
-			temp |= (0x3 << 16);
-			reg += 0x4;
-			ret = regmap_write(regmap, reg, temp);
+static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
+				     int pin_num, int strength)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 
-			return ret;
-		case 18 ... 21:
-			/* setting fully enclosed in the second register */
-			reg += 4;
-			bit -= 16;
-			break;
-		default:
-			debug("unsupported bit: %d for pinctrl drive type: %d\n",
-			      bit, drv_type);
-			return -EINVAL;
-		}
-		break;
-	case DRV_TYPE_IO_DEFAULT:
-	case DRV_TYPE_IO_1V8_OR_3V0:
-	case DRV_TYPE_IO_1V8_ONLY:
-		rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
-		break;
-	default:
-		debug("unsupported pinctrl drive type: %d\n",
-		      drv_type);
-		return -EINVAL;
-	}
+	debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
+	      pin_num, strength);
 
-	if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) {
-		regmap_read(regmap, reg, &data);
-		data &= ~(((1 << rmask_bits) - 1) << bit);
-	} else {
-		/* enable the write to the equivalent lower bits */
-		data = ((1 << rmask_bits) - 1) << (bit + 16);
-	}
+	if (!ctrl->set_drive)
+		return -ENOTSUPP;
 
-	data |= (ret << bit);
-	ret = regmap_write(regmap, reg, data);
-	return ret;
+	return ctrl->set_drive(bank, pin_num, strength);
 }
 
 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
@@ -359,70 +270,35 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
 	},
 };
 
+int rockchip_translate_pull_value(int type, int pull)
+{
+	int i, ret;
+
+	ret = -EINVAL;
+	for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
+		i++) {
+		if (rockchip_pull_list[type][i] == pull) {
+			ret = i;
+			break;
+		}
+	}
+
+	return ret;
+}
+
 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 			     int pin_num, int pull)
 {
 	struct rockchip_pinctrl_priv *priv = bank->priv;
 	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
-	struct regmap *regmap;
-	int reg, ret, i, pull_type;
-	u8 bit;
-	u32 data;
 
 	debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
 	      pin_num, pull);
 
-	ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
+	if (!ctrl->set_pull)
+		return -ENOTSUPP;
 
-	switch (ctrl->type) {
-	case RK3036:
-	case RK3128:
-		data = BIT(bit + 16);
-		if (pull == PIN_CONFIG_BIAS_DISABLE)
-			data |= BIT(bit);
-		ret = regmap_write(regmap, reg, data);
-		break;
-	case RV1108:
-	case RK3188:
-	case RK3288:
-	case RK3368:
-	case RK3399:
-		/*
-		 * Where need to clean the special mask for
-		 * rockchip_pull_list.
-		 */
-		pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK);
-		ret = -EINVAL;
-		for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
-			i++) {
-			if (rockchip_pull_list[pull_type][i] == pull) {
-				ret = i;
-				break;
-			}
-		}
-
-		if (ret < 0) {
-			debug("unsupported pull setting %d\n", pull);
-			return ret;
-		}
-
-		if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) {
-			regmap_read(regmap, reg, &data);
-			data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
-		} else {
-			/* enable the write to the equivalent lower bits */
-			data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
-		}
-
-		data |= (ret << bit);
-		ret = regmap_write(regmap, reg, data);
-		break;
-	default:
-		debug("unsupported pinctrl type\n");
-		return -EINVAL;
-	}
-
-	return ret;
+	return ctrl->set_pull(bank, pin_num, pull);
 }
 
 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
@@ -430,89 +306,40 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
 {
 	struct rockchip_pinctrl_priv *priv = bank->priv;
 	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
-	struct regmap *regmap;
-	int reg, ret;
-	u8 bit;
-	u32 data;
 
 	debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
 	      pin_num, enable);
 
-	ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
-	if (ret)
-		return ret;
-
-	/* enable the write to the equivalent lower bits */
-	data = BIT(bit + 16) | (enable << bit);
-
-	return regmap_write(regmap, reg, data);
-}
-
-/*
- * Pinconf_ops handling
- */
-static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
-					unsigned int pull)
-{
-	switch (ctrl->type) {
-	case RK3036:
-	case RK3128:
-		return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
-			pull == PIN_CONFIG_BIAS_DISABLE);
-	case RV1108:
-	case RK3188:
-	case RK3288:
-	case RK3368:
-	case RK3399:
-		return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
-	}
+	if (!ctrl->set_schmitt)
+		return -ENOTSUPP;
 
-	return false;
+	return ctrl->set_schmitt(bank, pin_num, enable);
 }
 
 /* set the pin config settings for a specified pin */
 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
 				u32 pin, u32 param, u32 arg)
 {
-	struct rockchip_pinctrl_priv *priv = bank->priv;
-	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 	int rc;
 
 	switch (param) {
 	case PIN_CONFIG_BIAS_DISABLE:
-		rc =  rockchip_set_pull(bank, pin, param);
-		if (rc)
-			return rc;
-		break;
-
 	case PIN_CONFIG_BIAS_PULL_UP:
 	case PIN_CONFIG_BIAS_PULL_DOWN:
 	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 	case PIN_CONFIG_BIAS_BUS_HOLD:
-		if (!rockchip_pinconf_pull_valid(ctrl, param))
-			return -ENOTSUPP;
-
-		if (!arg)
-			return -EINVAL;
-
 		rc = rockchip_set_pull(bank, pin, param);
 		if (rc)
 			return rc;
 		break;
 
 	case PIN_CONFIG_DRIVE_STRENGTH:
-		if (!ctrl->drv_calc_reg)
-			return -ENOTSUPP;
-
 		rc = rockchip_set_drive_perpin(bank, pin, arg);
 		if (rc < 0)
 			return rc;
 		break;
 
 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
-		if (!ctrl->schmitt_calc_reg)
-			return -ENOTSUPP;
-
 		rc = rockchip_set_schmitt(bank, pin, arg);
 		if (rc < 0)
 			return rc;
@@ -530,9 +357,8 @@ static const struct pinconf_param rockchip_conf_params[] = {
 	{ "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
 	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
 	{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+	{ "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
 	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
-	{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
-	{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
 	{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
 	{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
 };
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
index 5a6849c996..9651e9c7a6 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -8,16 +8,6 @@
 
 #include <linux/types.h>
 
-enum rockchip_pinctrl_type {
-	RV1108,
-	RK3036,
-	RK3128,
-	RK3188,
-	RK3288,
-	RK3368,
-	RK3399,
-};
-
 /**
  * Encode variants of iomux registers into a type variable
  */
@@ -26,7 +16,6 @@ enum rockchip_pinctrl_type {
 #define IOMUX_SOURCE_PMU	BIT(2)
 #define IOMUX_UNROUTED		BIT(3)
 #define IOMUX_WIDTH_3BIT	BIT(4)
-#define IOMUX_WRITABLE_32BIT	BIT(5)
 
 /**
  * Defined some common pins constants
@@ -50,9 +39,6 @@ struct rockchip_iomux {
 	int				offset;
 };
 
-#define DRV_TYPE_IO_MASK		GENMASK(31, 16)
-#define DRV_TYPE_WRITABLE_32BIT		BIT(31)
-
 /**
  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  */
@@ -65,9 +51,6 @@ enum rockchip_pin_drv_type {
 	DRV_TYPE_MAX
 };
 
-#define PULL_TYPE_IO_MASK		GENMASK(31, 16)
-#define PULL_TYPE_WRITABLE_32BIT	BIT(31)
-
 /**
  * enum type index corresponding to rockchip_pull_list arrays index.
  */
@@ -207,32 +190,6 @@ struct rockchip_pin_bank {
 		},							\
 	}
 
-#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1,	\
-				      iom2, iom3, drv0, drv1, drv2,	\
-				      drv3, pull0, pull1, pull2,	\
-				      pull3)				\
-	{								\
-		.bank_num	= id,					\
-		.nr_pins	= pins,					\
-		.name		= label,				\
-		.iomux		= {					\
-			{ .type = iom0, .offset = -1 },			\
-			{ .type = iom1, .offset = -1 },			\
-			{ .type = iom2, .offset = -1 },			\
-			{ .type = iom3, .offset = -1 },			\
-		},							\
-		.drv		= {					\
-			{ .drv_type = drv0, .offset = -1 },		\
-			{ .drv_type = drv1, .offset = -1 },		\
-			{ .drv_type = drv2, .offset = -1 },		\
-			{ .drv_type = drv3, .offset = -1 },		\
-		},							\
-		.pull_type[0] = pull0,					\
-		.pull_type[1] = pull1,					\
-		.pull_type[2] = pull2,					\
-		.pull_type[3] = pull3,					\
-	}
-
 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,	\
 					      label, iom0, iom1, iom2,  \
 					      iom3, drv0, drv1, drv2,   \
@@ -299,8 +256,6 @@ struct rockchip_pin_ctrl {
 	struct rockchip_pin_bank	*pin_banks;
 	u32				nr_banks;
 	u32				nr_pins;
-	char				*label;
-	enum rockchip_pinctrl_type	type;
 	int				grf_mux_offset;
 	int				pmu_mux_offset;
 	int				grf_drv_offset;
@@ -310,15 +265,14 @@ struct rockchip_pin_ctrl {
 	struct rockchip_mux_route_data *iomux_routes;
 	u32				niomux_routes;
 
-	void	(*pull_calc_reg)(struct rockchip_pin_bank *bank,
-				 int pin_num, struct regmap **regmap,
-				 int *reg, u8 *bit);
-	void	(*drv_calc_reg)(struct rockchip_pin_bank *bank,
-				int pin_num, struct regmap **regmap,
-				int *reg, u8 *bit);
-	int	(*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
-				    int pin_num, struct regmap **regmap,
-				    int *reg, u8 *bit);
+	int	(*set_mux)(struct rockchip_pin_bank *bank,
+			   int pin, int mux);
+	int	(*set_pull)(struct rockchip_pin_bank *bank,
+			    int pin_num, int pull);
+	int	(*set_drive)(struct rockchip_pin_bank *bank,
+			     int pin_num, int strength);
+	int	(*set_schmitt)(struct rockchip_pin_bank *bank,
+			       int pin_num, int enable);
 };
 
 /**
@@ -331,5 +285,12 @@ struct rockchip_pinctrl_priv {
 
 extern const struct pinctrl_ops rockchip_pinctrl_ops;
 int rockchip_pinctrl_probe(struct udevice *dev);
+void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
+			       int *reg, u8 *bit, int *mask);
+bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
+			    int mux, u32 *reg, u32 *value);
+int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask);
+int rockchip_translate_drive_value(int type, int strength);
+int rockchip_translate_pull_value(int type, int pull);
 
 #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */
diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c
index f4a09a6824..54610a3e90 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c
@@ -75,6 +75,33 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 	},
 };
 
+static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data;
+
+	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+				? priv->regmap_pmu : priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	if (bank->recalced_mask & BIT(pin))
+		rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RV1108_PULL_PMU_OFFSET		0x10
 #define RV1108_PULL_OFFSET		0x110
 
@@ -101,6 +128,34 @@ static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 	*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
 }
 
+static int rv1108_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
+
+	rv1108_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RV1108_DRV_PMU_OFFSET		0x20
 #define RV1108_DRV_GRF_OFFSET		0x210
 
@@ -128,6 +183,30 @@ static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 }
 
+static int rv1108_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data;
+	u8 bit;
+	int type = bank->drv[pin_num / 8].drv_type;
+
+	rv1108_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ret = rockchip_translate_drive_value(type, strength);
+	if (ret < 0) {
+		debug("unsupported driver strength %d\n", strength);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+	return ret;
+}
+
 #define RV1108_SCHMITT_PMU_OFFSET		0x30
 #define RV1108_SCHMITT_GRF_OFFSET		0x388
 #define RV1108_SCHMITT_BANK_STRIDE		8
@@ -158,6 +237,21 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
 	return 0;
 }
 
+static int rv1108_set_schmitt(struct rockchip_pin_bank *bank,
+			      int pin_num, int enable)
+{
+	struct regmap *regmap;
+	int reg;
+	u8 bit;
+	u32 data;
+
+	rv1108_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	/* enable the write to the equivalent lower bits */
+	data = BIT(bit + 16) | (enable << bit);
+
+	return regmap_write(regmap, reg, data);
+}
+
 static struct rockchip_pin_bank rv1108_pin_banks[] = {
 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
 					     IOMUX_SOURCE_PMU,
@@ -171,15 +265,14 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
 	.pin_banks		= rv1108_pin_banks,
 	.nr_banks		= ARRAY_SIZE(rv1108_pin_banks),
-	.label			= "RV1108-GPIO",
-	.type			= RV1108,
 	.grf_mux_offset		= 0x10,
 	.pmu_mux_offset		= 0x0,
 	.iomux_recalced		= rv1108_mux_recalced_data,
 	.niomux_recalced	= ARRAY_SIZE(rv1108_mux_recalced_data),
-	.pull_calc_reg		= rv1108_calc_pull_reg_and_bit,
-	.drv_calc_reg		= rv1108_calc_drv_reg_and_bit,
-	.schmitt_calc_reg	= rv1108_calc_schmitt_reg_and_bit,
+	.set_mux		= rv1108_set_mux,
+	.set_pull		= rv1108_set_pull,
+	.set_drive		= rv1108_set_drive,
+	.set_schmitt		= rv1108_set_schmitt,
 };
 
 static const struct udevice_id rv1108_pinctrl_ids[] = {
diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index 92f584fadc..e52fc3baad 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -842,7 +842,11 @@ static int setup_sdram(struct udevice *dev)
 	move_to_access_state(pctl);
 
 	/* TODO(prt): could detect rank in training... */
+#ifdef CONFIG_TARGET_EVB_PX5
+	params->chan.rank = 1;
+#else
 	params->chan.rank = 2;
+#endif
 	/* TODO(prt): bus width is not auto-detected (yet)... */
 	params->chan.bw = 2;  /* 32bit wide bus */
 	params->chan.dbw = params->chan.dbw;  /* 32bit wide bus */
diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c
index c596523d4f..e96ac54c39 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -49,7 +49,7 @@ struct rk322x_sdram_params {
 		struct regmap *map;
 };
 
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
 /*
  * [7:6]  bank(n:n bit bank)
  * [5:4]  row(13+n)
@@ -750,7 +750,7 @@ static int rk322x_dmc_ofdata_to_platdata(struct udevice *dev)
 
 	return 0;
 }
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_TPL_BUILD */
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 static int conv_of_platdata(struct udevice *dev)
@@ -778,7 +778,7 @@ static int conv_of_platdata(struct udevice *dev)
 
 static int rk322x_dmc_probe(struct udevice *dev)
 {
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
 	struct rk322x_sdram_params *plat = dev_get_platdata(dev);
 	int ret;
 	struct udevice *dev_clk;
@@ -786,7 +786,7 @@ static int rk322x_dmc_probe(struct udevice *dev)
 	struct dram_info *priv = dev_get_priv(dev);
 
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	ret = conv_of_platdata(dev);
 	if (ret)
@@ -842,12 +842,12 @@ U_BOOT_DRIVER(dmc_rk322x) = {
 	.id = UCLASS_RAM,
 	.of_match = rk322x_dmc_ids,
 	.ops = &rk322x_dmc_ops,
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
 	.ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata,
 #endif
 	.probe = rk322x_dmc_probe,
 	.priv_auto_alloc_size = sizeof(struct dram_info),
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
 	.platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params),
 #endif
 };
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 05ec5fc28d..52518656c4 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -30,7 +30,8 @@ struct chan_info {
 };
 
 struct dram_info {
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 	struct chan_info chan[2];
 	struct clk ddr_clk;
 	struct rk3399_cru *cru;
@@ -55,7 +56,8 @@ struct dram_info {
 #define PHY_DRV_ODT_40		0xe
 #define PHY_DRV_ODT_34_3	0xf
 
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 
 struct rockchip_dmc_plat {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
@@ -1187,7 +1189,8 @@ static int rk3399_dmc_init(struct udevice *dev)
 
 static int rk3399_dmc_probe(struct udevice *dev)
 {
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 	if (rk3399_dmc_init(dev))
 		return 0;
 #else
@@ -1226,12 +1229,14 @@ U_BOOT_DRIVER(dmc_rk3399) = {
 	.id = UCLASS_RAM,
 	.of_match = rk3399_dmc_ids,
 	.ops = &rk3399_dmc_ops,
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 	.ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
 #endif
 	.probe = rk3399_dmc_probe,
 	.priv_auto_alloc_size = sizeof(struct dram_info),
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 	.platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
 #endif
 };
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 8ce3e2e207..d456f0ce36 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -13,6 +13,24 @@ config SYSRESET
 	  to effect a reset. The uclass will try all available drivers when
 	  reset_walk() is called.
 
+config SPL_SYSRESET
+	bool "Enable support for system reset drivers in SPL mode"
+	depends on SYSRESET && SPL_DM
+	help
+	  Enable system reset drivers which can be used to reset the CPU or
+	  board. Each driver can provide a reset method which will be called
+	  to effect a reset. The uclass will try all available drivers when
+	  reset_walk() is called.
+
+config TPL_SYSRESET
+	bool "Enable support for system reset drivers in TPL mode"
+	depends on SYSRESET && TPL_DM
+	help
+	  Enable system reset drivers which can be used to reset the CPU or
+	  board. Each driver can provide a reset method which will be called
+	  to effect a reset. The uclass will try all available drivers when
+	  reset_walk() is called.
+
 if SYSRESET
 
 config SYSRESET_GPIO
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index b3728ac17f..8e1c845dfe 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -2,7 +2,7 @@
 #
 # (C) Copyright 2016 Cadence Design Systems Inc.
 
-obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o
 obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
 obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
 obj-$(CONFIG_ARCH_STI) += sysreset_sti.o