diff options
| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2017-09-26 20:34:35 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-04-11 23:11:58 +0200 |
| commit | 78773f1467336f4d874a6de8e56a5092b786fde5 (patch) | |
| tree | 256bce0922fe3b34ebe2578b4610c4844181d86e /drivers | |
| parent | f98833dbe61e8784f6c7afed8f5ff9290973d211 (diff) | |
| download | u-boot-78773f1467336f4d874a6de8e56a5092b786fde5.tar.gz | |
mmc: matsushita-common: Handle Renesas div-by-1
On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/matsushita-common.c | 3 | ||||
| -rw-r--r-- | drivers/mmc/matsushita-common.h | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/drivers/mmc/matsushita-common.c b/drivers/mmc/matsushita-common.c index 449f533d1b..7e05b1f3d1 100644 --- a/drivers/mmc/matsushita-common.c +++ b/drivers/mmc/matsushita-common.c @@ -542,7 +542,8 @@ static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv, divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); if (divisor <= 1) - val = MATSU_SD_CLKCTL_DIV1; + val = (priv->caps & MATSU_SD_CAP_RCAR) ? + MATSU_SD_CLKCTL_RCAR_DIV1 : MATSU_SD_CLKCTL_DIV1; else if (divisor <= 2) val = MATSU_SD_CLKCTL_DIV2; else if (divisor <= 4) diff --git a/drivers/mmc/matsushita-common.h b/drivers/mmc/matsushita-common.h index c23dc1a79a..a10ad202c8 100644 --- a/drivers/mmc/matsushita-common.h +++ b/drivers/mmc/matsushita-common.h @@ -63,6 +63,7 @@ #define MATSU_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ #define MATSU_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ #define MATSU_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ +#define MATSU_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */ #define MATSU_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ #define MATSU_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ #define MATSU_SD_SIZE 0x04c /* block size */ |