Merge tag 'mips-pull-2021-04-24' of https://source.denx.de/u-boot/custodians/u-boot-mipsWIP/24Apr2021

- MIPS: octeon: fix minor bugs of initial merge
- MIPS: octeon: add support for QLM and PCI-E controller
- MIPS: octeon: add support for AHCI and SATA
- MIPS: octeon: add E1000 ethernet support
- MIPS: octeon: add Octeon III NIC23 board
- ata/scsi: add support for Big Endian platforms

13 files changed, 781 insertions, 42 deletions

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 9ff4b8736c..b5a279862a 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -116,7 +116,7 @@ config SUNXI_AHCI
 
 config AHCI_MVEBU
 	bool "Marvell EBU AHCI SATA support"
-	depends on ARCH_MVEBU
+	depends on ARCH_MVEBU || ARCH_OCTEON
 	depends on AHCI
 	select SCSI_AHCI
 	select DM_SCSI
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 98b288254b..57c4e153ba 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -500,6 +500,7 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
 {
 	struct ahci_ioports *pp = &(uc_priv->port[port]);
 	struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
+	phys_addr_t pa = virt_to_phys(buf);
 	u32 sg_count;
 	int i;
 
@@ -510,9 +511,6 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
 	}
 
 	for (i = 0; i < sg_count; i++) {
-		/* We assume virt=phys */
-		phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT;
-
 		ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
 		ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
 		if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
@@ -520,25 +518,26 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
 			return -1;
 		}
 		ahci_sg->flags_size = cpu_to_le32(0x3fffff &
-					  (buf_len < MAX_DATA_BYTE_COUNT
-					   ? (buf_len - 1)
-					   : (MAX_DATA_BYTE_COUNT - 1)));
+					  (buf_len < MAX_DATA_BYTE_COUNT ?
+					   (buf_len - 1) :
+					   (MAX_DATA_BYTE_COUNT - 1)));
 		ahci_sg++;
 		buf_len -= MAX_DATA_BYTE_COUNT;
+		pa += MAX_DATA_BYTE_COUNT;
 	}
 
 	return sg_count;
 }
 
-
 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
 {
+	phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl);
+
 	pp->cmd_slot->opts = cpu_to_le32(opts);
 	pp->cmd_slot->status = 0;
-	pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
+	pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa));
 #ifdef CONFIG_PHYS_64BIT
-	pp->cmd_slot->tbl_addr_hi =
-	    cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
+	pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa));
 #endif
 }
 
@@ -674,12 +673,12 @@ static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
 
 	ahci_dcache_invalidate_range((unsigned long)buf,
 				     (unsigned long)buf_len);
-	debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
+	debug("%s: %d byte transferred.\n", __func__,
+	      le32_to_cpu(pp->cmd_slot->status));
 
 	return 0;
 }
 
-
 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
 {
 	int i;
diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index 7d82d2ea3f..f05150d61d 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_mvebu.c
@@ -39,7 +39,7 @@ static int mvebu_ahci_probe(struct udevice *dev)
 	 */
 	board_ahci_enable();
 
-	ahci_probe_scsi(dev, dev_read_addr(dev));
+	ahci_probe_scsi(dev, (ulong)dev_remap_addr(dev));
 
 	return 0;
 }
@@ -48,6 +48,7 @@ static const struct udevice_id mvebu_ahci_ids[] = {
 	{ .compatible = "marvell,armada-380-ahci" },
 	{ .compatible = "marvell,armada-3700-ahci" },
 	{ .compatible = "marvell,armada-8k-ahci" },
+	{ .compatible = "cavium,octeon-7130-ahci" },
 	{ }
 };
 
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index cdcdd8f456..d5b6018b3d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -158,6 +158,12 @@ config PCI_OCTEONTX
 	  These controllers provide PCI configuration access to all on-board
 	  peripherals so it should only be disabled for testing purposes
 
+config PCIE_OCTEON
+	bool "MIPS Octeon PCIe support"
+	depends on ARCH_OCTEON
+	help
+	  Enable support for the MIPS Octeon SoC family PCIe controllers.
+
 config PCI_XILINX
 	bool "Xilinx AXI Bridge for PCI Express"
 	depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 96d61821fe..1f741786a0 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o
 obj-$(CONFIG_PCIE_DW_MESON) += pcie_dw_meson.o
 obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
 obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
+obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
diff --git a/drivers/pci/pcie_octeon.c b/drivers/pci/pcie_octeon.c
new file mode 100644
index 0000000000..3b28bd8143
--- /dev/null
+++ b/drivers/pci/pcie_octeon.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <pci.h>
+#include <linux/delay.h>
+
+#include <mach/octeon-model.h>
+#include <mach/octeon_pci.h>
+#include <mach/cvmx-regs.h>
+#include <mach/cvmx-pcie.h>
+#include <mach/cvmx-pemx-defs.h>
+
+struct octeon_pcie {
+	void *base;
+	int first_busno;
+	u32 port;
+	struct udevice *dev;
+	int pcie_port;
+};
+
+static bool octeon_bdf_invalid(pci_dev_t bdf, int first_busno)
+{
+	/*
+	 * In PCIe only a single device (0) can exist on the local bus.
+	 * Beyound the local bus, there might be a switch and everything
+	 * is possible.
+	 */
+	if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
+		return true;
+
+	return false;
+}
+
+static int pcie_octeon_write_config(struct udevice *bus, pci_dev_t bdf,
+				    uint offset, ulong value,
+				    enum pci_size_t size)
+{
+	struct octeon_pcie *pcie = dev_get_priv(bus);
+	struct pci_controller *hose = dev_get_uclass_priv(bus);
+	int busno;
+	int port;
+
+	debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
+	      PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+	debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
+
+	port = pcie->pcie_port;
+	busno = PCI_BUS(bdf) - hose->first_busno + 1;
+
+	switch (size) {
+	case PCI_SIZE_8:
+		cvmx_pcie_config_write8(port, busno, PCI_DEV(bdf),
+					PCI_FUNC(bdf), offset, value);
+		break;
+	case PCI_SIZE_16:
+		cvmx_pcie_config_write16(port, busno, PCI_DEV(bdf),
+					 PCI_FUNC(bdf), offset, value);
+		break;
+	case PCI_SIZE_32:
+		cvmx_pcie_config_write32(port, busno, PCI_DEV(bdf),
+					 PCI_FUNC(bdf), offset, value);
+		break;
+	default:
+		printf("Invalid size\n");
+	};
+
+	return 0;
+}
+
+static int pcie_octeon_read_config(const struct udevice *bus, pci_dev_t bdf,
+				   uint offset, ulong *valuep,
+				   enum pci_size_t size)
+{
+	struct octeon_pcie *pcie = dev_get_priv(bus);
+	struct pci_controller *hose = dev_get_uclass_priv(bus);
+	int busno;
+	int port;
+
+	port = pcie->pcie_port;
+	busno = PCI_BUS(bdf) - hose->first_busno + 1;
+	if (octeon_bdf_invalid(bdf, pcie->first_busno)) {
+		*valuep = pci_get_ff(size);
+		return 0;
+	}
+
+	switch (size) {
+	case PCI_SIZE_8:
+		*valuep = cvmx_pcie_config_read8(port, busno, PCI_DEV(bdf),
+						 PCI_FUNC(bdf), offset);
+		break;
+	case PCI_SIZE_16:
+		*valuep = cvmx_pcie_config_read16(port, busno, PCI_DEV(bdf),
+						  PCI_FUNC(bdf), offset);
+		break;
+	case PCI_SIZE_32:
+		*valuep = cvmx_pcie_config_read32(port, busno, PCI_DEV(bdf),
+						  PCI_FUNC(bdf), offset);
+		break;
+	default:
+		printf("Invalid size\n");
+	};
+
+	debug("%02x.%02x.%02x: u%d %x -> %lx\n",
+	      PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep);
+
+	return 0;
+}
+
+static int pcie_octeon_probe(struct udevice *dev)
+{
+	struct octeon_pcie *pcie = dev_get_priv(dev);
+	int node = cvmx_get_node_num();
+	int pcie_port;
+	int ret = 0;
+
+	/* Get port number, lane number and memory target / attr */
+	if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
+			    &pcie->port)) {
+		ret = -ENODEV;
+		goto err;
+	}
+
+	pcie->first_busno = dev_seq(dev);
+	pcie_port = ((node << 4) | pcie->port);
+	ret = cvmx_pcie_rc_initialize(pcie_port);
+	if (ret != 0)
+		return ret;
+
+	return 0;
+
+err:
+	return ret;
+}
+
+static const struct dm_pci_ops pcie_octeon_ops = {
+	.read_config = pcie_octeon_read_config,
+	.write_config = pcie_octeon_write_config,
+};
+
+static const struct udevice_id pcie_octeon_ids[] = {
+	{ .compatible = "marvell,pcie-host-octeon" },
+	{ }
+};
+
+U_BOOT_DRIVER(pcie_octeon) = {
+	.name		= "pcie_octeon",
+	.id		= UCLASS_PCI,
+	.of_match	= pcie_octeon_ids,
+	.ops		= &pcie_octeon_ops,
+	.probe		= pcie_octeon_probe,
+	.priv_auto	= sizeof(struct octeon_pcie),
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/ram/octeon/octeon3_lmc.c b/drivers/ram/octeon/octeon3_lmc.c
index 327cdc5873..349abc179f 100644
--- a/drivers/ram/octeon/octeon3_lmc.c
+++ b/drivers/ram/octeon/octeon3_lmc.c
@@ -17,14 +17,8 @@
 
 /* Random number generator stuff */
 
-#define CVMX_RNM_CTL_STATUS	0x0001180040000000
 #define CVMX_OCT_DID_RNG	8ULL
 
-static u64 cvmx_build_io_address(u64 major_did, u64 sub_did)
-{
-	return ((0x1ull << 48) | (major_did << 43) | (sub_did << 40));
-}
-
 static u64 cvmx_rng_get_random64(void)
 {
 	return csr_rd(cvmx_build_io_address(CVMX_OCT_DID_RNG, 0));
@@ -285,10 +279,10 @@ static int test_dram_byte64(struct ddr_priv *priv, int lmc, u64 p,
 	int node = 0;
 
 	// Force full cacheline write-backs to boost traffic
-	l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+	l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
 	saved_dissblkdty = l2c_ctl.cn78xx.dissblkdty;
 	l2c_ctl.cn78xx.dissblkdty = 1;
-	l2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64);
+	l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64);
 
 	if (octeon_is_cpuid(OCTEON_CN73XX) || octeon_is_cpuid(OCTEON_CNF75XX))
 		kbitno = 18;
@@ -489,9 +483,9 @@ static int test_dram_byte64(struct ddr_priv *priv, int lmc, u64 p,
 	}
 
 	// Restore original setting that could enable partial cacheline writes
-	l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+	l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
 	l2c_ctl.cn78xx.dissblkdty = saved_dissblkdty;
-	l2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64);
+	l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64);
 
 	return errors;
 }
@@ -6315,17 +6309,17 @@ static void lmc_final(struct ddr_priv *priv)
 	lmc_rd(priv, CVMX_LMCX_INT(if_num));
 
 	for (tad = 0; tad < num_tads; tad++) {
-		l2c_wr(priv, CVMX_L2C_TADX_INT(tad),
-		       l2c_rd(priv, CVMX_L2C_TADX_INT(tad)));
+		l2c_wr(priv, CVMX_L2C_TADX_INT_REL(tad),
+		       l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad)));
 		debug("%-45s : (%d) 0x%08llx\n", "CVMX_L2C_TAD_INT", tad,
-		      l2c_rd(priv, CVMX_L2C_TADX_INT(tad)));
+		      l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad)));
 	}
 
 	for (mci = 0; mci < num_mcis; mci++) {
-		l2c_wr(priv, CVMX_L2C_MCIX_INT(mci),
-		       l2c_rd(priv, CVMX_L2C_MCIX_INT(mci)));
+		l2c_wr(priv, CVMX_L2C_MCIX_INT_REL(mci),
+		       l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci)));
 		debug("%-45s : (%d) 0x%08llx\n", "L2C_MCI_INT", mci,
-		      l2c_rd(priv, CVMX_L2C_MCIX_INT(mci)));
+		      l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci)));
 	}
 
 	debug("%-45s : 0x%08llx\n", "LMC_INT",
@@ -9827,7 +9821,7 @@ static void cvmx_dram_address_extract_info(struct ddr_priv *priv, u64 address,
 		address -= ADDRESS_HOLE;
 
 	/* Determine the LMC controllers */
-	l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+	l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
 
 	/* xbits depends on number of LMCs */
 	xbits = cvmx_dram_get_num_lmc(priv) >> 1;	// 4->2, 2->1, 1->0
diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
index 1f75dc15fa..e7b61d39f5 100644
--- a/drivers/ram/octeon/octeon_ddr.c
+++ b/drivers/ram/octeon/octeon_ddr.c
@@ -145,7 +145,7 @@ static void cvmx_l2c_set_big_size(struct ddr_priv *priv, u64 mem_size, int mode)
 		big_ctl.u64 = 0;
 		big_ctl.s.maxdram = bits - 9;
 		big_ctl.cn61xx.disable = mode;
-		l2c_wr(priv, CVMX_L2C_BIG_CTL, big_ctl.u64);
+		l2c_wr(priv, CVMX_L2C_BIG_CTL_REL, big_ctl.u64);
 	}
 }
 
@@ -2274,15 +2274,15 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz,
 		printf("Disabling L2 ECC based on disable_l2_ecc environment variable\n");
 		union cvmx_l2c_ctl l2c_val;
 
-		l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+		l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
 		l2c_val.s.disecc = 1;
-		l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);
+		l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);
 	} else {
 		union cvmx_l2c_ctl l2c_val;
 
-		l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+		l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
 		l2c_val.s.disecc = 0;
-		l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);
+		l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);
 	}
 
 	/*
@@ -2295,17 +2295,17 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz,
 
 		puts("L2 index aliasing disabled.\n");
 
-		l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+		l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
 		l2c_val.s.disidxalias = 1;
-		l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);
+		l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);
 	} else {
 		union cvmx_l2c_ctl l2c_val;
 
 		/* Enable L2C index aliasing */
 
-		l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+		l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
 		l2c_val.s.disidxalias = 0;
-		l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);
+		l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);
 	}
 
 	if (OCTEON_IS_OCTEON3()) {
@@ -2321,7 +2321,7 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz,
 		u64 rdf_cnt;
 		char *s;
 
-		l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+		l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
 
 		/*
 		 * It is more convenient to compute the ratio using clock
@@ -2338,7 +2338,7 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz,
 		debug("%-45s : %d, cpu_hertz:%d, ddr_hertz:%d\n",
 		      "EARLY FILL COUNT  ", l2c_ctl.cn78xx.rdf_cnt, cpu_hertz,
 		      ddr_hertz);
-		l2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64);
+		l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64);
 	}
 
 	/* Check for lower DIMM socket populated */
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 7389484490..ce69750c7f 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -9,6 +9,7 @@
 #include <bootstage.h>
 #include <dm.h>
 #include <env.h>
+#include <libata.h>
 #include <log.h>
 #include <part.h>
 #include <pci.h>
@@ -594,6 +595,11 @@ static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose)
 	memcpy(&bdesc->vendor, &bd.vendor, sizeof(bd.vendor));
 	memcpy(&bdesc->product, &bd.product, sizeof(bd.product));
 	memcpy(&bdesc->revision, &bd.revision,	sizeof(bd.revision));
+	if (IS_ENABLED(CONFIG_SYS_BIG_ENDIAN)) {
+		ata_swap_buf_le16((u16 *)&bdesc->vendor, sizeof(bd.vendor) / 2);
+		ata_swap_buf_le16((u16 *)&bdesc->product, sizeof(bd.product) / 2);
+		ata_swap_buf_le16((u16 *)&bdesc->revision, sizeof(bd.revision) / 2);
+	}
 
 	if (verbose) {
 		printf("  Device %d: ", bdesc->devnum);
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index af83e9673a..6d1c4530dd 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -788,6 +788,30 @@ config MSM_SERIAL
 	  for example APQ8016 and MSM8916.
 	  Single baudrate is supported in current implementation (115200).
 
+config OCTEON_SERIAL_BOOTCMD
+	bool "MIPS Octeon PCI remote bootcmd input"
+	depends on ARCH_OCTEON
+	depends on DM_SERIAL
+	select SYS_IS_IN_ENV
+	select CONSOLE_MUX
+	help
+	 This driver supports remote input over the PCIe bus from a host
+	 to U-Boot for entering commands.  It is utilized by the host
+	 commands 'oct-remote-load' and 'oct-remote-bootcmd'.
+
+config OCTEON_SERIAL_PCIE_CONSOLE
+	bool "MIPS Octeon PCIe remote console"
+	depends on ARCH_OCTEON
+	depends on (DM_SERIAL && DM_STDIO)
+	select SYS_STDIO_DEREGISTER
+	select SYS_CONSOLE_IS_IN_ENV
+	select CONSOLE_MUX
+	help
+	  This driver supports remote console over the PCIe bus when the
+	  Octeon is running in PCIe target mode. The host program
+	  'oct-remote-console' can be used to connect to this console.
+	  The console number will likely be 0 or 1.
+
 config OMAP_SERIAL
 	bool "Support for OMAP specific UART"
 	depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 92bcb30b85..6c0fdca586 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -66,6 +66,8 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
 obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
 obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
 obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
+obj-$(CONFIG_OCTEON_SERIAL_BOOTCMD) += serial_octeon_bootcmd.o
+obj-$(CONFIG_OCTEON_SERIAL_PCIE_CONSOLE) += serial_octeon_pcie_console.o
 obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
 obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
 obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
diff --git a/drivers/serial/serial_octeon_bootcmd.c b/drivers/serial/serial_octeon_bootcmd.c
new file mode 100644
index 0000000000..4bcff77eb8
--- /dev/null
+++ b/drivers/serial/serial_octeon_bootcmd.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ * Copyright (C) 2021 Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <dm/uclass.h>
+#include <errno.h>
+#include <input.h>
+#include <iomux.h>
+#include <log.h>
+#include <serial.h>
+#include <stdio_dev.h>
+#include <string.h>
+#include <watchdog.h>
+#include <linux/delay.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <mach/cvmx-regs.h>
+#include <mach/cvmx-bootmem.h>
+
+#define DRIVER_NAME				"pci-bootcmd"
+
+/*
+ * Important:
+ * This address cannot be changed as the PCI console tool relies on exactly
+ * this value!
+ */
+#define BOOTLOADER_PCI_READ_BUFFER_BASE		0x6c000
+#define BOOTLOADER_PCI_READ_BUFFER_SIZE		256
+#define BOOTLOADER_PCI_WRITE_BUFFER_SIZE	256
+
+#define BOOTLOADER_PCI_READ_BUFFER_STR_LEN	\
+	(BOOTLOADER_PCI_READ_BUFFER_SIZE - 8)
+#define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN	\
+	(BOOTLOADER_PCI_WRITE_BUFFER_SIZE - 8)
+
+#define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR	\
+	(BOOTLOADER_PCI_READ_BUFFER_BASE + 0)
+#define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR	\
+	(BOOTLOADER_PCI_READ_BUFFER_BASE + 4)
+#define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR	\
+	(BOOTLOADER_PCI_READ_BUFFER_BASE + 8)
+
+enum octeon_pci_io_buf_owner {
+	/* Must be zero, set when memory cleared */
+	OCTEON_PCI_IO_BUF_OWNER_INVALID = 0,
+	OCTEON_PCI_IO_BUF_OWNER_OCTEON = 1,
+	OCTEON_PCI_IO_BUF_OWNER_HOST = 2,
+};
+
+/* Structure for bootloader PCI IO buffers */
+struct octeon_pci_io_buf {
+	u32 owner;
+	u32 len;
+	char data[0];
+};
+
+struct octeon_bootcmd_priv {
+	bool started;
+	int copy_offset;
+	bool eol;
+	bool unlocked;
+	struct octeon_pci_io_buf *buf;
+};
+
+static int octeon_bootcmd_pending(struct udevice *dev, bool input)
+{
+	struct octeon_bootcmd_priv *priv = dev_get_priv(dev);
+
+	if (!input)
+		return 0;
+
+	if (priv->eol)
+		return 1;
+
+	CVMX_SYNC;
+	if (priv->buf->owner != OCTEON_PCI_IO_BUF_OWNER_OCTEON)
+		return 0;
+
+	if (priv->buf->len > priv->copy_offset &&
+	    (priv->buf->data[priv->copy_offset] != '\0'))
+		return 1;
+
+	return 0;
+}
+
+static int octeon_bootcmd_getc(struct udevice *dev)
+{
+	struct octeon_bootcmd_priv *priv = dev_get_priv(dev);
+	char c;
+
+	/* There's no EOL for boot commands so we fake it. */
+	if (priv->eol) {
+		priv->eol = false;
+		return '\n';
+	}
+
+	while (!octeon_bootcmd_pending(dev, true)) {
+		WATCHDOG_RESET();
+		/*
+		 * ToDo:
+		 * The original code calls octeon_board_poll() here. We may
+		 * need to implement something similar here.
+		 */
+		udelay(100);
+	}
+
+	c = priv->buf->data[priv->copy_offset];
+	priv->buf->data[priv->copy_offset++] = '\0';
+
+	if (priv->copy_offset >= min_t(int, CONFIG_SYS_CBSIZE - 1,
+				       BOOTLOADER_PCI_READ_BUFFER_STR_LEN - 1) ||
+	    (priv->buf->data[priv->copy_offset] == '\0')) {
+		priv->copy_offset = 0;
+		priv->buf->len = 0;
+		priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_HOST;
+		priv->eol = true;
+		CVMX_SYNC;
+	}
+
+	return c;
+}
+
+static const struct dm_serial_ops octeon_bootcmd_ops = {
+	.getc = octeon_bootcmd_getc,
+	.pending = octeon_bootcmd_pending,
+};
+
+static int octeon_bootcmd_probe(struct udevice *dev)
+{
+	struct octeon_bootcmd_priv *priv = dev_get_priv(dev);
+
+	priv->buf = (void *)CKSEG0ADDR(BOOTLOADER_PCI_READ_BUFFER_BASE);
+	memset(priv->buf, 0, BOOTLOADER_PCI_READ_BUFFER_SIZE);
+	priv->eol = false;
+
+	/*
+	 * When the bootcmd console is first started it is started as locked to
+	 * block any calls sending a command until U-Boot is ready to accept
+	 * commands.  Just before the main loop starts to accept commands the
+	 * bootcmd console is unlocked.
+	 */
+	if (priv->unlocked)
+		priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_HOST;
+	else
+		priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_OCTEON;
+
+	debug("%s called, buffer ptr: 0x%p, owner: %s\n", __func__,
+	      priv->buf,
+	      priv->buf->owner == OCTEON_PCI_IO_BUF_OWNER_HOST ?
+	      "host" : "octeon");
+	debug("&priv->copy_offset: 0x%p\n", &priv->copy_offset);
+	CVMX_SYNC;
+
+	/*
+	 * Perhaps reinvestige this: In the original code, "unlocked" etc
+	 * is set in the octeon_pci_bootcmd_unlock() function called very
+	 * late.
+	 */
+	priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_HOST;
+	priv->unlocked = true;
+	priv->started = true;
+	CVMX_SYNC;
+
+	return 0;
+}
+
+static const struct udevice_id octeon_bootcmd_serial_id[] = {
+	{ .compatible = "marvell,pci-bootcmd", },
+	{ },
+};
+
+U_BOOT_DRIVER(octeon_bootcmd) = {
+	.name = DRIVER_NAME,
+	.id = UCLASS_SERIAL,
+	.ops = &octeon_bootcmd_ops,
+	.of_match = of_match_ptr(octeon_bootcmd_serial_id),
+	.probe = octeon_bootcmd_probe,
+	.priv_auto = sizeof(struct octeon_bootcmd_priv),
+};
diff --git a/drivers/serial/serial_octeon_pcie_console.c b/drivers/serial/serial_octeon_pcie_console.c
new file mode 100644
index 0000000000..c76e787d03
--- /dev/null
+++ b/drivers/serial/serial_octeon_pcie_console.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ * Copyright (C) 2021 Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <dm/uclass.h>
+#include <errno.h>
+#include <input.h>
+#include <iomux.h>
+#include <log.h>
+#include <serial.h>
+#include <stdio_dev.h>
+#include <string.h>
+#include <watchdog.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <mach/cvmx-regs.h>
+#include <mach/cvmx-bootmem.h>
+
+#define DRIVER_NAME				"pci-console"
+#define OCTEONTX_PCIE_CONSOLE_NAME_LEN		16
+
+/* Current versions */
+#define OCTEON_PCIE_CONSOLE_MAJOR_VERSION	1
+#define OCTEON_PCIE_CONSOLE_MINOR_VERSION	0
+
+#define OCTEON_PCIE_CONSOLE_BLOCK_NAME		"__pci_console"
+
+/*
+ * Structure that defines a single console.
+ * Note: when read_index == write_index, the buffer is empty.
+ * The actual usable size of each console is console_buf_size -1;
+ */
+struct octeon_pcie_console {
+	u64 input_base_addr;
+	u32 input_read_index;
+	u32 input_write_index;
+	u64 output_base_addr;
+	u32 output_read_index;
+	u32 output_write_index;
+	u32 lock;
+	u32 buf_size;
+};
+
+/*
+ * This is the main container structure that contains all the information
+ * about all PCI consoles. The address of this structure is passed to various
+ * routines that operation on PCI consoles.
+ */
+struct octeon_pcie_console_desc {
+	u32 major_version;
+	u32 minor_version;
+	u32 lock;
+	u32 flags;
+	u32 num_consoles;
+	u32 pad;
+	/* must be 64 bit aligned here... */
+	/* Array of addresses of octeon_pcie_console_t structures */
+	u64 console_addr_array[0];
+	/* Implicit storage for console_addr_array */
+};
+
+struct octeon_pcie_console_priv {
+	struct octeon_pcie_console *console;
+	int console_num;
+	bool console_active;
+};
+
+/* Flag definitions for read/write functions */
+enum {
+	/*
+	 * If set, read/write functions won't block waiting for space or data.
+	 * For reads, 0 bytes may be read, and for writes not all of the
+	 * supplied data may be written.
+	 */
+	OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0,
+};
+
+static int buffer_free_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx)
+{
+	if (rd_idx >= buffer_size || wr_idx >= buffer_size)
+		return -1;
+
+	return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size;
+}
+
+static int buffer_avail_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx)
+{
+	if (rd_idx >= buffer_size || wr_idx >= buffer_size)
+		return -1;
+
+	return buffer_size - 1 - buffer_free_bytes(buffer_size, wr_idx, rd_idx);
+}
+
+static int buffer_read_avail(struct udevice *dev, unsigned int console_num)
+{
+	struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+	struct octeon_pcie_console *cons_ptr = priv->console;
+	int avail;
+
+	avail = buffer_avail_bytes(cons_ptr->buf_size,
+				   cons_ptr->input_write_index,
+				   cons_ptr->input_read_index);
+	if (avail >= 0)
+		return avail;
+
+	return 0;
+}
+
+static int octeon_pcie_console_read(struct udevice *dev,
+				    unsigned int console_num, char *buffer,
+				    int buffer_size, u32 flags)
+{
+	struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+	struct octeon_pcie_console *cons_ptr = priv->console;
+	int avail;
+	char *buf_ptr;
+	int bytes_read;
+	int read_size;
+
+	buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->input_base_addr);
+
+	avail =	buffer_avail_bytes(cons_ptr->buf_size,
+				   cons_ptr->input_write_index,
+				   cons_ptr->input_read_index);
+	if (avail < 0)
+		return avail;
+
+	if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK)) {
+		/* Wait for some data to be available */
+		while (0 == (avail = buffer_avail_bytes(cons_ptr->buf_size,
+							cons_ptr->input_write_index,
+							cons_ptr->input_read_index))) {
+			mdelay(10);
+			WATCHDOG_RESET();
+		}
+	}
+
+	bytes_read = 0;
+
+	/* Don't overflow the buffer passed to us */
+	read_size = min_t(int, avail, buffer_size);
+
+	/* Limit ourselves to what we can input in a contiguous block */
+	if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size)
+		read_size = cons_ptr->buf_size - cons_ptr->input_read_index;
+
+	memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size);
+	cons_ptr->input_read_index =
+		(cons_ptr->input_read_index + read_size) % cons_ptr->buf_size;
+	bytes_read += read_size;
+
+	/* Mark the PCIe console to be active from now on */
+	if (bytes_read)
+		priv->console_active = true;
+
+	return bytes_read;
+}
+
+static int octeon_pcie_console_write(struct udevice *dev,
+				     unsigned int console_num,
+				     const char *buffer,
+				     int bytes_to_write, u32 flags)
+{
+	struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+	struct octeon_pcie_console *cons_ptr = priv->console;
+	int avail;
+	char *buf_ptr;
+	int bytes_written;
+
+	buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->output_base_addr);
+	bytes_written = 0;
+	while (bytes_to_write > 0) {
+		avail = buffer_free_bytes(cons_ptr->buf_size,
+					  cons_ptr->output_write_index,
+					  cons_ptr->output_read_index);
+
+		if (avail > 0) {
+			int write_size = min_t(int, avail, bytes_to_write);
+
+			/*
+			 * Limit ourselves to what we can output in a contiguous
+			 * block
+			 */
+			if (cons_ptr->output_write_index + write_size >=
+			    cons_ptr->buf_size) {
+				write_size = cons_ptr->buf_size -
+					     cons_ptr->output_write_index;
+			}
+
+			memcpy(buf_ptr + cons_ptr->output_write_index,
+			       buffer + bytes_written, write_size);
+			/*
+			 * Make sure data is visible before changing write
+			 * index
+			 */
+			CVMX_SYNCW;
+			cons_ptr->output_write_index =
+				(cons_ptr->output_write_index + write_size) %
+				cons_ptr->buf_size;
+			bytes_to_write -= write_size;
+			bytes_written += write_size;
+		} else if (avail == 0) {
+			/*
+			 * Check to see if we should wait for room, or return
+			 * after a partial write
+			 */
+			if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
+				goto done;
+
+			WATCHDOG_RESET();
+			mdelay(10);	/* Delay if we are spinning */
+		} else {
+			bytes_written = -1;
+			goto done;
+		}
+	}
+
+done:
+	return bytes_written;
+}
+
+static struct octeon_pcie_console_desc *octeon_pcie_console_init(int num_consoles,
+								 int buffer_size)
+{
+	struct octeon_pcie_console_desc *cons_desc_ptr;
+	struct octeon_pcie_console *cons_ptr;
+	s64 addr;
+	u64 avail_addr;
+	int alloc_size;
+	int i;
+
+	/* Compute size required for pci console structure */
+	alloc_size = num_consoles *
+		(buffer_size * 2 + sizeof(struct octeon_pcie_console) +
+		 sizeof(u64)) + sizeof(struct octeon_pcie_console_desc);
+
+	/*
+	 * Allocate memory for the consoles.  This must be in the range
+	 * addresssible by the bootloader.
+	 * Try to do so in a manner which minimizes fragmentation.  We try to
+	 * put it at the top of DDR0 or bottom of DDR2 first, and only do
+	 * generic allocation if those fail
+	 */
+	addr = cvmx_bootmem_phy_named_block_alloc(alloc_size,
+						  OCTEON_DDR0_SIZE - alloc_size - 128,
+						  OCTEON_DDR0_SIZE, 128,
+						  OCTEON_PCIE_CONSOLE_BLOCK_NAME,
+						  CVMX_BOOTMEM_FLAG_END_ALLOC);
+	if (addr < 0) {
+		addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0,
+							  0x1fffffff, 128,
+							  OCTEON_PCIE_CONSOLE_BLOCK_NAME,
+							  CVMX_BOOTMEM_FLAG_END_ALLOC);
+	}
+	if (addr < 0)
+		return 0;
+
+	cons_desc_ptr = cvmx_phys_to_ptr(addr);
+
+	/* Clear entire alloc'ed memory */
+	memset(cons_desc_ptr, 0, alloc_size);
+
+	/* Initialize as locked until we are done */
+	cons_desc_ptr->lock = 1;
+	CVMX_SYNCW;
+	cons_desc_ptr->num_consoles = num_consoles;
+	cons_desc_ptr->flags = 0;
+	cons_desc_ptr->major_version = OCTEON_PCIE_CONSOLE_MAJOR_VERSION;
+	cons_desc_ptr->minor_version = OCTEON_PCIE_CONSOLE_MINOR_VERSION;
+
+	avail_addr = addr + sizeof(struct octeon_pcie_console_desc) +
+		num_consoles * sizeof(u64);
+
+	for (i = 0; i < num_consoles; i++) {
+		cons_desc_ptr->console_addr_array[i] = avail_addr;
+		cons_ptr = (void *)cons_desc_ptr->console_addr_array[i];
+		avail_addr += sizeof(struct octeon_pcie_console);
+		cons_ptr->input_base_addr = avail_addr;
+		avail_addr += buffer_size;
+		cons_ptr->output_base_addr = avail_addr;
+		avail_addr += buffer_size;
+		cons_ptr->buf_size = buffer_size;
+	}
+	CVMX_SYNCW;
+	cons_desc_ptr->lock = 0;
+
+	return cvmx_phys_to_ptr(addr);
+}
+
+static int octeon_pcie_console_getc(struct udevice *dev)
+{
+	char c;
+
+	octeon_pcie_console_read(dev, 0, &c, 1, 0);
+	return c;
+}
+
+static int octeon_pcie_console_putc(struct udevice *dev, const char c)
+{
+	struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+
+	if (priv->console_active)
+		octeon_pcie_console_write(dev, 0, (char *)&c, 1, 0);
+
+	return 0;
+}
+
+static int octeon_pcie_console_pending(struct udevice *dev, bool input)
+{
+	if (input) {
+		udelay(100);
+		return buffer_read_avail(dev, 0) > 0;
+	}
+
+	return 0;
+}
+
+static const struct dm_serial_ops octeon_pcie_console_ops = {
+	.getc = octeon_pcie_console_getc,
+	.putc = octeon_pcie_console_putc,
+	.pending = octeon_pcie_console_pending,
+};
+
+static int octeon_pcie_console_probe(struct udevice *dev)
+{
+	struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+	struct octeon_pcie_console_desc *cons_desc;
+	int console_count;
+	int console_size;
+	int console_num;
+
+	/*
+	 * Currently only 1 console is supported. Perhaps we need to add
+	 * a console nexus if more than one needs to be supported.
+	 */
+	console_count = 1;
+	console_size = 1024;
+	console_num = 0;
+
+	cons_desc = octeon_pcie_console_init(console_count, console_size);
+	priv->console =
+		cvmx_phys_to_ptr(cons_desc->console_addr_array[console_num]);
+
+	debug("PCI console init succeeded, %d consoles, %d bytes each\n",
+	      console_count, console_size);
+
+	return 0;
+}
+
+static const struct udevice_id octeon_pcie_console_serial_id[] = {
+	{ .compatible = "marvell,pci-console", },
+	{ },
+};
+
+U_BOOT_DRIVER(octeon_pcie_console) = {
+	.name = DRIVER_NAME,
+	.id = UCLASS_SERIAL,
+	.ops = &octeon_pcie_console_ops,
+	.of_match = of_match_ptr(octeon_pcie_console_serial_id),
+	.probe = octeon_pcie_console_probe,
+	.priv_auto = sizeof(struct octeon_pcie_console_priv),
+};