diff options
| author | Vasili Galka <vvv444@gmail.com> | 2014-03-09 15:56:52 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-03-12 16:22:12 -0400 |
| commit | ce6889a9978822172c50c92744f0ff11138e3e37 (patch) | |
| tree | 2023de2263b434a7b32b4b3b45e859e50523acc8 /drivers/spi | |
| parent | d73f38f7ba4d8a6309b4c35830e46935c4cd6a55 (diff) | |
| download | u-boot-ce6889a9978822172c50c92744f0ff11138e3e37.tar.gz | |
drivers/spi/omap3: Bug fix of premature write transfer completion
The logic determining SPI "write" transfer completion was faulty. At
certain conditions (e.g. slow SPI clock freq) the transfers were
interrupted before completion. Both EOT and TXS flags of channel
status registeer shall be checked to ensure that all data was
transferred. Tested on AM3359 chip.
Signed-off-by: Vasili Galka <vasili@visionmap.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/omap3_spi.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index a3ad056473..651e46e4bd 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -260,8 +260,9 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp, } /* wait to finish of transfer */ - while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & - OMAP3_MCSPI_CHSTAT_EOT)); + while ((readl(&ds->regs->channel[ds->slave.cs].chstat) & + (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) != + (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)); /* Disable the channel otherwise the next immediate RX will get affected */ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); |