diff options
| author | Vignesh R <vigneshr@ti.com> | 2016-07-06 10:20:56 +0530 |
|---|---|---|
| committer | Jagan Teki <jteki@openedev.com> | 2016-07-09 20:16:33 +0530 |
| commit | 2372e14f1937fceea54d698342e5a4240b58a893 (patch) | |
| tree | ff5362dd329b3f2e970bc77368641fd9a9f49fde /drivers/spi | |
| parent | dac3bf20fb2c9b03476be0d73db620f62ab3cee1 (diff) | |
| download | u-boot-2372e14f1937fceea54d698342e5a4240b58a893.tar.gz | |
spi: cadence_quadspi: Enable QUAD mode based on DT data
Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine
whether to enable or disable QUAD mode. This is necessary to support
muliple SPI controllers where one of them may not support QUAD mode.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 3 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.h | 2 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 10 |
3 files changed, 8 insertions, 7 deletions
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 4f7fd52532..a5244fff4d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -191,6 +191,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, struct udevice *bus = dev->parent; struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev); void *base = priv->regbase; u8 *cmd_buf = priv->cmd_buf; size_t data_bytes; @@ -250,7 +251,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, break; case CQSPI_INDIRECT_READ: err = cadence_qspi_apb_indirect_read_setup(plat, - priv->cmd_len, cmd_buf); + priv->cmd_len, dm_plat->mode_rx, cmd_buf); if (!err) { err = cadence_qspi_apb_indirect_read_execute (plat, data_bytes, din); diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 2912e36a53..a849f7b199 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -53,7 +53,7 @@ int cadence_qspi_apb_command_write(void *reg_base_addr, unsigned int txlen, const u8 *txbuf); int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, - unsigned int cmdlen, const u8 *cmdbuf); + unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf); int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, unsigned int rxlen, u8 *rxbuf); int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index a8cc23f0b6..1a35d558a6 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -29,6 +29,7 @@ #include <asm/io.h> #include <asm/errno.h> #include <wait_bit.h> +#include <spi.h> #include "cadence_qspi.h" #define CQSPI_REG_POLL_US (1) /* 1us */ @@ -548,7 +549,7 @@ int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen, /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, - unsigned int cmdlen, const u8 *cmdbuf) + unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf) { unsigned int reg; unsigned int rd_reg; @@ -578,10 +579,9 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, /* Configure the opcode */ rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; -#if (CONFIG_SPI_FLASH_QUAD == 1) - /* Instruction and address at DQ0, data at DQ0-3. */ - rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; -#endif + if (rx_width & SPI_RX_QUAD) + /* Instruction and address at DQ0, data at DQ0-3. */ + rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; /* Get address */ addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); |