diff options
| author | Simon Glass <sjg@chromium.org> | 2020-05-10 11:40:10 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-18 21:19:23 -0400 |
| commit | 07e1114671c8b13d1bb90548a3c5ea31c49415d1 (patch) | |
| tree | d64c8a76ebfe729975a5b5a9e0b9f56bfdec01fb /drivers/rtc | |
| parent | 1af3c7f422f627a544fec13e436d1a7975e39e73 (diff) | |
| download | u-boot-07e1114671c8b13d1bb90548a3c5ea31c49415d1.tar.gz | |
Fix some checkpatch warnings in calls to udelay()
Fix up some incorrect code style in calls to functions in the linux/time.h
header, mostly udelay().
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/rtc')
| -rw-r--r-- | drivers/rtc/ds1306.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c index 02d617e09c..1bd1151e1b 100644 --- a/drivers/rtc/ds1306.c +++ b/drivers/rtc/ds1306.c @@ -71,7 +71,7 @@ int rtc_get (struct rtc_time *tmp) /* Now we can enable the DS1306 RTC */ immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay (10); + udelay(10); /* Shift out the address (0) of the time in the Clock Chip */ soft_spi_send (0); @@ -105,7 +105,7 @@ int rtc_get (struct rtc_time *tmp) /* Now we can disable the DS1306 RTC */ immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay (10); + udelay(10); rtc_calc_weekday(tmp); /* Determine the day of week */ @@ -127,7 +127,7 @@ int rtc_set (struct rtc_time *tmp) /* Now we can enable the DS1306 RTC */ immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay (10); + udelay(10); /* First disable write protect in the clock chip control register */ soft_spi_send (0x8F); /* send address of the control register */ @@ -135,11 +135,11 @@ int rtc_set (struct rtc_time *tmp) /* Now disable the DS1306 to terminate the write */ immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; - udelay (10); + udelay(10); /* Now enable the DS1306 to initiate a new write */ immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay (10); + udelay(10); /* Next, send the address of the clock time write registers */ soft_spi_send (0x80); /* send address of the first time register */ @@ -156,11 +156,11 @@ int rtc_set (struct rtc_time *tmp) /* Now we can disable the Clock chip to terminate the burst write */ immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay (10); + udelay(10); /* Now we can enable the Clock chip to initiate a new write */ immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay (10); + udelay(10); /* First we Enable write protect in the clock chip control register */ soft_spi_send (0x8F); /* send address of the control register */ @@ -168,7 +168,7 @@ int rtc_set (struct rtc_time *tmp) /* Now disable the DS1306 */ immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay (10); + udelay(10); /* Set standard MPC8xx clock to the same time so Linux will * see the time even if it doesn't have a DS1306 clock driver. @@ -204,7 +204,7 @@ static void init_spi (void) immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK); immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */ - udelay (10); + udelay(10); } /* ------------------------------------------------------------------------- */ @@ -227,10 +227,10 @@ static void soft_spi_send (unsigned char n) immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */ else immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */ - udelay (10); + udelay(10); immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay (10); + udelay(10); bitpos >>= 1; /* Shift for next bit position */ } @@ -253,11 +253,11 @@ static unsigned char soft_spi_read (void) /* Read 8 bits here */ for (i = 0; i < 8; i++) { /* Do 8 bits in loop */ immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - udelay (10); + udelay(10); if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */ spi_byte |= bitpos; /* Set data accordingly */ immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay (10); + udelay(10); bitpos >>= 1; /* Shift for next bit position */ } |