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authorHaiying Wang <Haiying.Wang@freescale.com>2009-05-21 15:34:14 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-06-12 17:16:59 -0500
commit7211fbfa18f3061858696150ee6e9e093d9eceae (patch)
tree6be78918f7bc3679ab9327b4859812eafae342ff /drivers/qe
parentb3d7f20f43a0f8d11c65e2f92153b5512b11580c (diff)
downloadu-boot-7211fbfa18f3061858696150ee6e9e093d9eceae.tar.gz
drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and define MAX_QE_RISC for QE based silicons. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/qe')
-rw-r--r--drivers/qe/qe.c3
-rw-r--r--drivers/qe/qe.h17
-rw-r--r--drivers/qe/uec.c32
-rw-r--r--drivers/qe/uec.h4
4 files changed, 44 insertions, 12 deletions
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 918bfa748e..f5096228d0 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -258,9 +258,6 @@ int qe_set_mii_clk_src(int ucc_num)
return 0;
}
-/* The maximum number of RISCs we support */
-#define MAX_QE_RISC 2
-
/* Firmware information stored here for qe_get_firmware_info() */
static struct qe_firmware_info qe_firmware_info;
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index d78edba23e..2128f5697e 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
@@ -46,11 +46,16 @@ typedef struct qe_snum {
/* QE RISC allocation
*/
-typedef enum qe_risc_allocation {
- QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
- QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
- QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */
-} qe_risc_allocation_e;
+#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
+#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
+#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
+#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
+#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
+ QE_RISC_ALLOCATION_RISC2)
+#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
+ QE_RISC_ALLOCATION_RISC2 | \
+ QE_RISC_ALLOCATION_RISC3 | \
+ QE_RISC_ALLOCATION_RISC4)
/* QE CECR commands for UCC fast.
*/
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index e67c0bab64..d02c8c98e8 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC4_PHY_ADDR,
@@ -138,8 +158,13 @@ static uec_info_t eth5_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC5_PHY_ADDR,
@@ -161,8 +186,13 @@ static uec_info_t eth6_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address = CONFIG_SYS_UEC6_PHY_ADDR,
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 414982cdec..4fd10962c9 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -654,8 +654,8 @@ typedef struct uec_info {
ucc_fast_info_t uf_info;
uec_num_of_threads_e num_threads_tx;
uec_num_of_threads_e num_threads_rx;
- qe_risc_allocation_e risc_tx;
- qe_risc_allocation_e risc_rx;
+ unsigned int risc_tx;
+ unsigned int risc_rx;
u16 rx_bd_ring_len;
u16 tx_bd_ring_len;
u8 phy_address;