diff options
| author | Priyanka Jain <priyanka.jain@nxp.com> | 2017-04-27 15:08:06 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-05-23 09:40:23 -0700 |
| commit | e809e747996b00acd0ffc833999e97a3a21ddfac (patch) | |
| tree | e62a9b5249c07df67dba198d2bdf6943a93fae14 /drivers/pci/pcie_layerscape.h | |
| parent | 89a168f776cbc15a2ff1f25a0f4e54f9bbaffdec (diff) | |
| download | u-boot-e809e747996b00acd0ffc833999e97a3a21ddfac.tar.gz | |
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/pci/pcie_layerscape.h')
| -rw-r--r-- | drivers/pci/pcie_layerscape.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index e3324a5e52..308b073f2b 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver * @@ -117,6 +118,8 @@ #define SVR_LS2084A 0x870910 #define SVR_LS2048A 0x870920 #define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870919 +#define SVR_LS2041A 0x870915 /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL |