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| author | Xiaowei Bao <xiaowei.bao@nxp.com> | 2020-07-09 23:31:41 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-07-27 14:24:15 +0530 |
| commit | 4085e3a46a86c10398ceb29e7a90f9345bc85b16 (patch) | |
| tree | 9e4b7d379021a907b229d3efcc647d164cf64dc3 /drivers/pci/pcie_layerscape.h | |
| parent | 80b5a662b7565928c97be9bc6e0a455e7f29dc75 (diff) | |
| download | u-boot-4085e3a46a86c10398ceb29e7a90f9345bc85b16.tar.gz | |
pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2
Add the PCIe EP mode support for lx2160a-v2 platform.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'drivers/pci/pcie_layerscape.h')
| -rw-r--r-- | drivers/pci/pcie_layerscape.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 5f5c51d3d6..593798e3e3 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -100,7 +100,7 @@ #define PCIE_SRIOV_VFBAR0 0x19C -#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x20000 * (pf))) +#define PCIE_MASK_OFFSET(flag, pf, off) ((flag) ? 0 : (0x1000 + (off) * (pf))) /* LUT registers */ #define PCIE_LUT_UDR(n) (0x800 + (n) * 8) @@ -139,6 +139,12 @@ #define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) #define LS1021_LTSSM_STATE_SHIFT 20 +/* LX2160a PF1 offset */ +#define LX2160_PCIE_PF1_OFFSET 0x8000 + +/* layerscape PF1 offset */ +#define LS_PCIE_PF1_OFFSET 0x20000 + struct ls_pcie { void __iomem *dbi; void __iomem *lut; @@ -170,6 +176,7 @@ struct ls_pcie_ep { void __iomem *addr; u32 cfg2_flag; u32 sriov_flag; + u32 pf1_offset; u32 num_ib_wins; u32 num_ob_wins; u8 max_functions; |