Merge tag 'xilinx-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into nextWIP/07Apr2020-next

Xilinx changes for v2020.07

common:
- Align ENV_FAT_INTERFACE
- Fix MAC address source print log
- Improve based autodetection code

xilinx:
- Enable netconsole

Microblaze:
- Setup default ENV_OFFSET/ENV_SECT_SIZE

Zynq:
- Multiple DT updates/fixes
- Use DEVICE_TREE environment variable for DTB selection
- Switch to single zynq configuration
- Enable NOR flash via DM
- Minor SPL print removal
- Enable i2c mux driver

ZynqMP:
- Print multiboot register
- Enable cache commands in mini mtest
- Multiple DT updates/fixes
- Fix firmware probing when driver is not enabled
- Specify 3rd backup RAM boot mode in SPL
- Add SPL support for zcu102 v1.1 and zcu111 revA
- Redesign debug uart enabling and psu_init delay
- Enable full u-boot run from EL3
- Enable u-boot.itb generation without ATF with U-Boot in EL3

Versal:
- Enable distro default
- Enable others SPI flashes
- Enable systems without DDR

Drivers:
- Gem:
  - Flush memory after freeing
  - Handle mdio bus separately
- Watchdog:
  - Get rid of unused global data pointer
  - Enable window watchdog timer
- Serial:
  - Change reinitialization logic in zynq serial driver

Signed-off-by: Tom Rini <trini@konsulko.com>

1 files changed, 33 insertions, 4 deletions

diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c
index c875f3a5b7..890b6a8fb6 100644
--- a/drivers/pci/pcie_ecam_generic.c
+++ b/drivers/pci/pcie_ecam_generic.c
@@ -19,6 +19,8 @@
  */
 struct generic_ecam_pcie {
 	void *cfg_base;
+	pci_size_t size;
+	int first_busno;
 };
 
 /**
@@ -43,7 +45,7 @@ static int pci_generic_ecam_conf_address(const struct udevice *bus,
 	void *addr;
 
 	addr = pcie->cfg_base;
-	addr += PCI_BUS(bdf) << 20;
+	addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
 	addr += PCI_DEV(bdf) << 15;
 	addr += PCI_FUNC(bdf) << 12;
 	addr += offset;
@@ -52,6 +54,16 @@ static int pci_generic_ecam_conf_address(const struct udevice *bus,
 	return 0;
 }
 
+static bool pci_generic_ecam_addr_valid(const struct udevice *bus,
+					pci_dev_t bdf)
+{
+	struct generic_ecam_pcie *pcie = dev_get_priv(bus);
+	int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
+
+	return (PCI_BUS(bdf) >= pcie->first_busno &&
+		PCI_BUS(bdf) < pcie->first_busno + num_buses);
+}
+
 /**
  * pci_generic_ecam_read_config() - Read from configuration space
  * @bus: Pointer to the PCI bus
@@ -68,6 +80,11 @@ static int pci_generic_ecam_read_config(const struct udevice *bus,
 					pci_dev_t bdf, uint offset,
 					ulong *valuep, enum pci_size_t size)
 {
+	if (!pci_generic_ecam_addr_valid(bus, bdf)) {
+		*valuep = pci_get_ff(size);
+		return 0;
+	}
+
 	return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
 					    bdf, offset, valuep, size);
 }
@@ -88,6 +105,9 @@ static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
 				    uint offset, ulong value,
 				    enum pci_size_t size)
 {
+	if (!pci_generic_ecam_addr_valid(bus, bdf))
+		return 0;
+
 	return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,
 					     bdf, offset, value, size);
 }
@@ -116,9 +136,17 @@ static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev)
 		return err;
 	}
 
-	pcie->cfg_base = map_physmem(reg_res.start,
-				     fdt_resource_size(&reg_res),
-				     MAP_NOCACHE);
+	pcie->size = fdt_resource_size(&reg_res);
+	pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
+
+	return 0;
+}
+
+static int pci_generic_ecam_probe(struct udevice *dev)
+{
+	struct generic_ecam_pcie *pcie = dev_get_priv(dev);
+
+	pcie->first_busno = dev->seq;
 
 	return 0;
 }
@@ -138,6 +166,7 @@ U_BOOT_DRIVER(pci_generic_ecam) = {
 	.id			= UCLASS_PCI,
 	.of_match		= pci_generic_ecam_ids,
 	.ops			= &pci_generic_ecam_ops,
+	.probe			= pci_generic_ecam_probe,
 	.ofdata_to_platdata	= pci_generic_ecam_ofdata_to_platdata,
 	.priv_auto_alloc_size	= sizeof(struct generic_ecam_pcie),
 };