diff options
| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2014-04-08 10:55:49 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:49 -0700 |
| commit | 2ee6c52e229e1d0d1e78c3efbc67bc8bb868fb25 (patch) | |
| tree | 4e915a1581f60eaf33769e95bcc9125b3b6f9f10 /drivers/net | |
| parent | 896720ceb2cededcd1f25fa5f5ff23822bea466d (diff) | |
| download | u-boot-2ee6c52e229e1d0d1e78c3efbc67bc8bb868fb25.tar.gz | |
driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3
MDIO clock needs to be initialized in u-boot code for SoCs
having FMAN-v3(v3H or v3L) controller due to below reasons
-On SoCs that have FMAN-v3H like B4860, default value of
MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates
mdio clock too high (much higher than 2.5MHz), violating the
IEEE specs.
-On SOCs that have FMAN-v3L like T1040, default value of
MDIO_CLK_DIV bits is zero, so MDIO clock is disabled.
So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to
be properly initialized.
Also this type of initialization is generally done in
PBI(pre-bootloader) phase using rcw.But for chips like T1040
which support deep-sleep, such type of initialization cannot be
done in PBI phase due to the limitation that during deep-sleep
resume, FMAN (MDIO) registers are not accessible in PBI phase.
So, mdio clock initailization must be done as part of u-boot.
This initialization code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/fm/memac_phy.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 140e59b75c..2f4bc11a6c 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -133,5 +133,17 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) bus->priv = info->regs; + /* + * On some platforms like B4860, default value of MDIO_CLK_DIV bits + * in mdio_stat(mdio_cfg) register generates MDIO clock too high + * (much higher than 2.5MHz), violating the IEEE specs. + * On other platforms like T1040, default value of MDIO_CLK_DIV bits + * is zero, so MDIO clock is disabled. + * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to + * be properly initialized. + */ + setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat, + MDIO_STAT_CLKDIV(258)); + return mdio_register(bus); } |