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authorStefan Theil <stefan.theil@mixed-mode.de>2018-12-17 09:12:30 +0100
committerMichal Simek <michal.simek@xilinx.com>2019-01-24 10:03:42 +0100
commit10598580612cbaee2298bddd77e9a51df5a2943d (patch)
tree2d7a791fc89552ac221525a97c56fddbd09db0c9 /drivers/net/zynq_gem.c
parent0bf3f9cb2722e57a0afb37cb61af5ceaefcf70e0 (diff)
downloadu-boot-10598580612cbaee2298bddd77e9a51df5a2943d.tar.gz
zynq-gem: Use appropriate cache flush/invalidate for RX and TX
The cache was only flushed before *transmitting* packets, but not when receiving them, leading to an issue where new packets were handed to the receive handler with old contents in cache. This only happens when a lot of packets are received without sending packages every now and then. Also flushing the receive buffers in the transmit function makes no sense and can be removed. Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/net/zynq_gem.c')
-rw-r--r--drivers/net/zynq_gem.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 9bd79b198a..3bd0093b7a 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -570,11 +570,6 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup(len, ARCH_DMA_MINALIGN);
flush_dcache_range(addr, addr + size);
-
- addr = (ulong)priv->rxbuffers;
- addr &= ~(ARCH_DMA_MINALIGN - 1);
- size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
- flush_dcache_range(addr, addr + size);
barrier();
/* Start transmit */
@@ -621,6 +616,9 @@ static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
*packetp = (uchar *)(uintptr_t)addr;
+ invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
+ barrier();
+
return frame_len;
}
@@ -706,6 +704,9 @@ static int zynq_gem_probe(struct udevice *dev)
return -ENOMEM;
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
+ u32 addr = (ulong)priv->rxbuffers;
+ flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
+ barrier();
/* Align bd_space to MMU_SECTION_SHIFT */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);