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| author | Michal Simek <michal.simek@xilinx.com> | 2019-10-04 15:52:43 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2019-10-24 13:37:01 +0200 |
| commit | 6596270ecb5d74d5f997da0daa728e06d1f47029 (patch) | |
| tree | 21d5b8265b2fa0e02297c0ee8edae46b9362a3cc /drivers/fpga | |
| parent | 866225f394a9b3174d9ea39d2d19ac0d2c07a516 (diff) | |
| download | u-boot-6596270ecb5d74d5f997da0daa728e06d1f47029.tar.gz | |
arm64: versal: Rename versal_pm_request to xilinx_pm_request
Use generic name instead of Versal specific because this should be also
used on ZynqMP.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/versalpl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index 8337b8306d..4bcc213243 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -39,7 +39,7 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits(bin_buf); buf_hi = upper_32_bits(bin_buf); - ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, buf_hi, 0, ret_payload); if (ret) puts("PL FPGA LOAD fail\n"); |