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authorPeter Tyser <ptyser@xes-inc.com>2009-06-30 17:15:44 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-07-01 23:07:45 -0500
commit484919cf3351212ebf748b9b13ece1ddaf7e7d1c (patch)
treefcb32c083cfe882ecfbf11f11e133398f6a6ab6e /drivers/dma
parent51402ac12be9a0025f16db51fbde7c050a54e5fe (diff)
downloadu-boot-484919cf3351212ebf748b9b13ece1ddaf7e7d1c.tar.gz
fsl_dma: Fix Channel Start bug in dma_check()
The Channel Start (CS) bit in the Mode Register (MR) should actually be cleared as the comment in the code suggests. Previously, CS was being set, not cleared. Assuming normal operation of the DMA engine, this change shouldn't have any real affect. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/fsl_dma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index f3575af6d7..f05880230b 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -60,7 +60,7 @@ static uint dma_check(void) {
} while (status & FSL_DMA_SR_CB);
/* clear MR[CS] channel start bit */
- out_be32(&dma->mr, in_be32(&dma->mr) & FSL_DMA_MR_CS);
+ out_be32(&dma->mr, in_be32(&dma->mr) & ~FSL_DMA_MR_CS);
dma_sync();
if (status != 0)