diff options
| author | Peter Tyser <ptyser@xes-inc.com> | 2009-06-30 17:15:43 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-07-01 23:07:43 -0500 |
| commit | 51402ac12be9a0025f16db51fbde7c050a54e5fe (patch) | |
| tree | 4c3b3cbfcaba34400666752d00a7d361f98e06a7 /drivers/dma/fsl_dma.c | |
| parent | a730393a362741c318b21771b8d7b2647e546c3e (diff) | |
| download | u-boot-51402ac12be9a0025f16db51fbde7c050a54e5fe.tar.gz | |
fsl_dma: Add support for arbitrarily large transfers
Support DMA transfers larger than the DMA controller's limit of
(2 ^ 26 - 1) bytes
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/dma/fsl_dma.c')
| -rw-r--r-- | drivers/dma/fsl_dma.c | 40 |
1 files changed, 28 insertions, 12 deletions
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index 33ea8285eb..f3575af6d7 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -30,6 +30,9 @@ #include <asm/io.h> #include <asm/fsl_dma.h> +/* Controller can only transfer 2^26 - 1 bytes at a time */ +#define FSL_DMA_MAX_SIZE (0x3ffffff) + #if defined(CONFIG_MPC85xx) ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); #elif defined(CONFIG_MPC86xx) @@ -77,20 +80,33 @@ void dma_init(void) { int dma_xfer(void *dest, uint count, void *src) { volatile fsl_dma_t *dma = &dma_base->dma[0]; + uint xfer_size; - out_be32(&dma->dar, (uint) dest); - out_be32(&dma->sar, (uint) src); - out_be32(&dma->bcr, count); + while (count) { + xfer_size = MIN(FSL_DMA_MAX_SIZE, count); - /* Disable bandwidth control, use direct transfer mode */ - out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT); - dma_sync(); + out_be32(&dma->dar, (uint) dest); + out_be32(&dma->sar, (uint) src); + out_be32(&dma->bcr, xfer_size); - /* Start the transfer */ - out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | - FSL_DMA_MR_CTM_DIRECT | - FSL_DMA_MR_CS); - dma_sync(); + /* Disable bandwidth control, use direct transfer mode */ + out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT); + dma_sync(); + + /* Start the transfer */ + out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | + FSL_DMA_MR_CTM_DIRECT | + FSL_DMA_MR_CS); + + count -= xfer_size; + src += xfer_size; + dest += xfer_size; + + dma_sync(); + + if (dma_check()) + return -1; + } - return dma_check(); + return 0; } |