diff options
| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-03-16 13:50:23 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-05-17 09:26:53 -0700 |
| commit | 5fc62fe57097e195a8047859cd3c278a5d6790b6 (patch) | |
| tree | 1b22ea733a537daa1866c87543e5cdec7c08d432 /drivers/ddr | |
| parent | 4a68489e12313a7fa8740463dee0eea2985eb563 (diff) | |
| download | u-boot-5fc62fe57097e195a8047859cd3c278a5d6790b6.tar.gz | |
driver/ddr/fsl: Add workaround for erratum A-009801
The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/fsl/fsl_ddr_gen4.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 7cdb7008b4..1dc0631440 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -251,6 +251,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009801 + temp32 = ddr_in32(&ddr->debug[25]); + temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; + temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; + ddr_out32(&ddr->debug[25], temp32); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; tmp = ddr_in32(&ddr->debug[28]); |