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| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-04-16 22:04:39 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-04-17 22:20:16 +0200 |
| commit | 29873c74f367474faafd16376e2a9f404172fbdd (patch) | |
| tree | 774cc94f1d909f9046eea4b233d772572e5fad8b /drivers/ddr/altera/sequencer.c | |
| parent | ede6e7b64fbd3beef691f526d14e088583f74472 (diff) | |
| download | u-boot-29873c74f367474faafd16376e2a9f404172fbdd.tar.gz | |
arm: socfpga: move gen5 SDR driver to DM
To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.
This gets us rid of one ad-hoc call to socfpga_per_reset().
The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.
SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'drivers/ddr/altera/sequencer.c')
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 5e7a943b68..0e4526288e 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3705,12 +3705,19 @@ static void initialize_tracking(void) &sdr_reg_file->trk_rfsh); } -int sdram_calibration_full(void) +int sdram_calibration_full(struct socfpga_sdr *sdr) { struct param_type my_param; struct gbl_type my_gbl; u32 pass; + /* + * For size reasons, this file uses hard coded addresses. + * Check if we are called with the correct address. + */ + if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS) + return -ENODEV; + memset(&my_param, 0, sizeof(my_param)); memset(&my_gbl, 0, sizeof(my_gbl)); |