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| author | Tom Rini <trini@konsulko.com> | 2020-04-30 11:31:33 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-30 11:34:01 -0400 |
| commit | 6d7dacf726ca043a3f5487549bbfa506c990c813 (patch) | |
| tree | 0976c82eca83479ba9337f9a1824572ea0b9578e /drivers/clk | |
| parent | b9da77f1958aab4ec50ff2f095b40464ca2489dd (diff) | |
| parent | 27d706937a5c72f0414a540ca20fd36b4b72bda7 (diff) | |
| download | u-boot-6d7dacf726ca043a3f5487549bbfa506c990c813.tar.gz | |
Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2020.07-rc2
mmc:
- Fix dt property handling via generic function
clk:
- Fix versal watchdog clock setting
nand:
- Fix zynq nand command comparison
xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose
zynq:
- Kconfig alignments
- Fix nand cse configuration
zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk_versal.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index d3673a5c8b..075a08380d 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -503,6 +503,9 @@ static u64 versal_clock_calc(u32 clk_id) NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF) return versal_clock_ref(clk_id); + if (!parent_id) + return 0; + clk_rate = versal_clock_calc(parent_id); if (versal_clock_div(clk_id)) { @@ -526,7 +529,7 @@ static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate) NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT && ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) == NODE_CLASS_CLOCK) { - if (!versal_clock_gate(clk_id)) + if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id)) return -EINVAL; *clk_rate = versal_clock_calc(clk_id); return 0; |