diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-01-10 13:32:02 +0900 |
|---|---|---|
| committer | Jaehoon Chung <jh80.chung@samsung.com> | 2017-01-11 19:40:14 +0900 |
| commit | b1b1add38c8f8fc885e294b075fb0b10058c109c (patch) | |
| tree | f8c2706774f6b2d689472f2389cd6cab952a91b5 /doc | |
| parent | 505cf4750ae55e711663538b3ec7a294c08e7417 (diff) | |
| download | u-boot-b1b1add38c8f8fc885e294b075fb0b10058c109c.tar.gz | |
ARM: socfpga: remove unused CONFIG option and cleanup README.socfpga
CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH is defined in the socfpga_common.h,
but not referenced at all. Remove.
Also, clean-up the README.socfpga. CONFIG_MMC should not be defined
in the header since it was moved to Kconfig by commit c27269953b94
("mmc: complete unfinished move of CONFIG_MMC"). I see no grep hit
for the others.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.socfpga | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/doc/README.socfpga b/doc/README.socfpga index cfcbbfe379..92942c940b 100644 --- a/doc/README.socfpga +++ b/doc/README.socfpga @@ -14,12 +14,6 @@ socfpga_dw_mmc Here are macro and detailed configuration required to enable DesignWare SDMMC controller support within SOCFPGA -#define CONFIG_MMC --> To enable the SD MMC framework support - -#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) --> The base address of CSR register for DesignWare SDMMC controller - #define CONFIG_GENERIC_MMC -> Enable the generic MMC driver @@ -31,23 +25,3 @@ controller support within SOCFPGA #define CONFIG_SOCFPGA_DWMMC -> Enable the SOCFPGA specific driver for DesignWare SDMMC controller - -#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 --> The FIFO depth for SOCFPGA DesignWare SDMMC controller - -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 --> Phase-shifted clock of sdmmc_clk for controller to drive command and data to -the card to meet hold time requirements. SD clock is running at 50MHz and -drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time -is 135 / 360 * 20ns = 7.5ns. - -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 --> Phase-shifted clock of sdmmc_clk used to sample the command and data from -the card - -#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 --> Bus width of data line which either 1, 4 or 8 and based on board routing. - -#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 --> The clock rate to controller. Do note the controller have a wrapper which -divide the clock from PLL by 4. |