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| author | Tom Rini <trini@konsulko.com> | 2023-05-11 08:40:33 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-05-11 08:40:33 -0400 |
| commit | e94fbdd2729fdcd570035d43f67adda8e0dfc115 (patch) | |
| tree | fc4d5d6f989618994e0af5bb61f9918e4c8a7478 /doc/board/coreboot/coreboot.rst | |
| parent | 0a9a4384c1483a88776bca38e28f09be51161034 (diff) | |
| parent | b982f89c583c6c03f4d1f94d29991ccf691a0f7c (diff) | |
| download | u-boot-e94fbdd2729fdcd570035d43f67adda8e0dfc115.tar.gz | |
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Various fixes for Google chromebooks
- Various minor enhancements for coreboot
Diffstat (limited to 'doc/board/coreboot/coreboot.rst')
| -rw-r--r-- | doc/board/coreboot/coreboot.rst | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index 4a5f101cad..0fe95af56d 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -71,3 +71,32 @@ Memory map (typically redirects to 7ab10030 or similar) 500 Location of coreboot sysinfo table, used during startup ========== ================================================================== + + +Debug UART +---------- + +It is possible to enable the debug UART with coreboot. To do this, use the +info from the cbsysinfo command to locate the UART base. For example:: + + => cbsysinfo + ... + Serial I/O port: 00000000 + base : 00000000 + pointer : 767b51bc + type : 2 + base : fe03e000 + baud : 0d115200 + regwidth : 4 + input_hz : 0d1843200 + PCI addr : 00000010 + ... + +Here you can see that the UART base is fe03e000, regwidth is 4 (1 << 2) and the +input clock is 1843200. So you can add the following CONFIG options:: + + CONFIG_DEBUG_UART=y + CONFIG_DEBUG_UART_BASE=fe03e000 + CONFIG_DEBUG_UART_CLOCK=1843200 + CONFIG_DEBUG_UART_SHIFT=2 + CONFIG_DEBUG_UART_ANNOUNCE=y |