diff options
| author | Tom Rini <trini@konsulko.com> | 2015-09-17 17:00:08 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-09-17 17:00:08 -0400 |
| commit | 1fb8d7933924aa5deb7e722d64c1d9fc7f0b2b82 (patch) | |
| tree | 3078931eaf7785303e12478e0cfd27ce4731dcf7 /doc/README.x86 | |
| parent | 5779b862d148294cc496ae2d6652584601ffd16e (diff) | |
| parent | c6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef (diff) | |
| download | u-boot-1fb8d7933924aa5deb7e722d64c1d9fc7f0b2b82.tar.gz | |
Merge git://git.denx.de/u-boot-x86
Diffstat (limited to 'doc/README.x86')
| -rw-r--r-- | doc/README.x86 | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/doc/README.x86 b/doc/README.x86 index 5f9c46f05d..6cf293b11e 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -733,11 +733,36 @@ Example output: PCI_BDF(0, 3, 0) INTA PIRQA ... +Porting Hints +------------- + +Quark-specific considerations: + +To port U-Boot to other boards based on the Intel Quark SoC, a few things need +to be taken care of. The first important part is the Memory Reference Code (MRC) +parameters. Quark MRC supports memory-down configuration only. All these MRC +parameters are supplied via the board device tree. To get started, first copy +the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then +change these values by consulting board manuals or your hardware vendor. +Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h. +The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports, +but by default they are held in reset after power on. In U-Boot, PCIe +initialization is properly handled as per Quark's firmware writer guide. +In your board support codes, you need provide two routines to aid PCIe +initialization, which are board_assert_perst() and board_deassert_perst(). +The two routines need implement a board-specific mechanism to assert/deassert +PCIe PERST# pin. Care must be taken that in those routines that any APIs that +may trigger PCI enumeration process are strictly forbidden, as any access to +PCIe root port's configuration registers will cause system hang while it is +held in reset. For more details, check how they are implemented by the Intel +Galileo board support codes in board/intel/galileo/galileo.c. + TODO List --------- - Audio - Chrome OS verified boot - SMI and ACPI support, to provide platform info and facilities to Linux +- Desktop Management Interface (DMI) [15] support References ---------- @@ -755,3 +780,4 @@ References [12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf [14] doc/device-tree-bindings/misc/intel,irq-router.txt +[15] http://en.wikipedia.org/wiki/Desktop_Management_Interface |