diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2019-12-09 13:00:57 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-01-14 09:05:53 +0100 |
| commit | de79ca951255deba6d303a1fd3668072b24e81ab (patch) | |
| tree | 0cd4a6747b173d33e518c9d4f50d82befa6510cf /configs | |
| parent | 594254e7fed524860f858c16631b0e7079f74274 (diff) | |
| download | u-boot-de79ca951255deba6d303a1fd3668072b24e81ab.tar.gz | |
arm64: zynqmp: Add board_boot_order for MMC boot extension
In past SPL_ZYNQMP_TWO_SDHCI symbol was introduced to handle boards with
two sdhci controllers. The problem was that U-Boot is registering
controllers based on aliases in DT but bootmode targets specific controller
ID. That's why on boards with one "second" sdhci controller bootmode was
pointing to second controller(MMC2) but alias was setup to mmc0 (the first
controller). And SPL requires to point to mmc0 in this case.
Long time ago commit f101e4bd3703
("spl: add support for alternative boot device") added support for handling
multiple bootmodes in SPL. Use this functionality and setup second sdhci
controller as backup boot device.
Below is table with behavior:
HW/bootmode bootorder
sd0/sd0 mmc0/mmc1 (mmc1 never called)
sd1/sd1 mmc1/mmc0 (mmc0 fails and mmc1 is called)
sd0+sd1/sd0 mmc0/mmc1 (mmc1 never called)
sd0+sd1/sd1 mmc1/mmc0 (mmc0 never called)
All other bootmodes are not affected but order can be extended to cover
advance boot flows.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 1 | ||||
| -rw-r--r-- | configs/xilinx_zynqmp_p_a2197_00_revA_defconfig | 1 | ||||
| -rw-r--r-- | configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 |
3 files changed, 0 insertions, 3 deletions
diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 177558db41..280983d187 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -7,7 +7,6 @@ CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y diff --git a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig index ba2cbaba58..f206be8a31 100644 --- a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig +++ b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig @@ -9,7 +9,6 @@ CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y -CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 7731407118..62c3730515 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -6,7 +6,6 @@ CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ZYNQMP_USB=y -CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y |