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| author | Hugh Cole-Baker <sigmaris@gmail.com> | 2020-11-22 13:03:44 +0000 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-01-08 08:40:43 -0500 |
| commit | 92cb207af110855ee9ae132c638b3d289a53d930 (patch) | |
| tree | 621f02fa10533bf76cabc0b63c6b59b0fe1c1f15 /configs | |
| parent | b8c725e736cbc9b43c861a0884491df079b3e613 (diff) | |
| download | u-boot-92cb207af110855ee9ae132c638b3d289a53d930.tar.gz | |
rockchip: pinebook-pro: default to SPI bus 1 for SPI-flash
SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/pinebook-pro-rk3399_defconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 8fbd7280ac..a471c3e06a 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_DM_KEYBOARD=y @@ -49,6 +50,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y |