diff options
| author | Stefan Roese <sr@denx.de> | 2010-02-02 13:43:48 +0100 |
|---|---|---|
| committer | Ben Warren <biggerbadderben@gmail.com> | 2010-02-06 22:52:21 -0800 |
| commit | ab5a0dcb9c8f19e351fc33c5db91469bfb1d9438 (patch) | |
| tree | 97785becfaff93d98dd9d04f94312b1a71836a44 /common/miiphyutil.c | |
| parent | 4294b2485bf0e8d68c893190a96bb0e7856b12c4 (diff) | |
| download | u-boot-ab5a0dcb9c8f19e351fc33c5db91469bfb1d9438.tar.gz | |
net: Use 0.5 sec timeout in miiphy_reset() instead of counting loop
This patch fixes a problem I've notived on a buggy PPC4xx system. This
system has problems with the PHY MDIO communication and seemed to be
stuck/crashed in miiphy_reset(). But degugging revealed, that the CPU
didn't crash, but "only" hung in this counting loop for about 2 minutes.
This patch now uses a real timeout of 0.5 seconds (as mentioned in the
comment in miiphy_reset).
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Diffstat (limited to 'common/miiphyutil.c')
| -rw-r--r-- | common/miiphyutil.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 196ef4a7ba..856fbc70b8 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -293,7 +293,7 @@ int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, int miiphy_reset (char *devname, unsigned char addr) { unsigned short reg; - int loop_cnt; + int timeout = 500; if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { debug ("PHY status read failed\n"); @@ -311,13 +311,13 @@ int miiphy_reset (char *devname, unsigned char addr) * auto-clearing). This should happen within 0.5 seconds per the * IEEE spec. */ - loop_cnt = 0; reg = 0x8000; - while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) { - if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { - debug ("PHY status read failed\n"); - return (-1); + while (((reg & 0x8000) != 0) && timeout--) { + if (miiphy_read(devname, addr, PHY_BMCR, ®) != 0) { + debug("PHY status read failed\n"); + return -1; } + udelay(1000); } if ((reg & 0x8000) == 0) { return (0); |