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| author | Marek Vasut <marex@denx.de> | 2018-04-15 13:15:33 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-05-08 21:08:42 +0200 |
| commit | 662abc4fc5cba70bc261039c4579223de3fca2ed (patch) | |
| tree | 26d50d3186912c3e8d7613735392d132cbad712a /common/image.c | |
| parent | 34fc2a6edfeb5d28244bf4a36615d1fe984a7921 (diff) | |
| download | u-boot-662abc4fc5cba70bc261039c4579223de3fca2ed.tar.gz | |
image: socfpga: Add SFP image version 1 definition
Add support for the SoCFPGA header v1, which is used on Arria 10.
The layout of the v0 and v1 header is similar, yet there are a few
differences which make it incompatible with previous v0 header, so
add a new entry.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Diffstat (limited to 'common/image.c')
| -rw-r--r-- | common/image.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/common/image.c b/common/image.c index 4eae585218..1493c3a874 100644 --- a/common/image.c +++ b/common/image.c @@ -145,7 +145,8 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, - { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",}, + { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SoCFPGA CV/AV preloader",}, + { IH_TYPE_SOCFPGAIMAGE_V1, "socfpgaimage_v1", "Altera SoCFPGA A10 preloader",}, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",}, |