diff options
| author | York Sun <york.sun@nxp.com> | 2016-11-17 13:12:38 -0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-11-23 23:42:08 -0800 |
| commit | fedae6ebafa79555693e5af1953aacb637ec24b9 (patch) | |
| tree | 4e51f1ae0b5f8c5eda471d99f2e86e51be74df6e /board | |
| parent | 41c7b7b132ef2c828b0a856d55e383a8c596532b (diff) | |
| download | u-boot-fedae6ebafa79555693e5af1953aacb637ec24b9.tar.gz | |
powerpc: P1020MBG: Separate from P1_P2_RDB_PC in Kconfig
Use TARGET_P1020MBG instead of sharing with TARGET_P1_P2_RDB_PC to
simplify Kconfig and other macros.
Remove macro CONFIG_P1020MBG.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/p1_p2_rdb_pc/Kconfig | 3 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb_pc/ddr.c | 2 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb_pc/tlb.c | 4 |
3 files changed, 5 insertions, 4 deletions
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig index d3352d2856..2c45560d2e 100644 --- a/board/freescale/p1_p2_rdb_pc/Kconfig +++ b/board/freescale/p1_p2_rdb_pc/Kconfig @@ -1,4 +1,5 @@ -if TARGET_P1_P2_RDB_PC +if TARGET_P1_P2_RDB_PC || \ + TARGET_P1020MBG config SYS_BOARD default "p1_p2_rdb_pc" diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 1f3793b853..a121256bf7 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -78,7 +78,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 30000, }; -#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD)) /* Micron MT41J512M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 2, diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 1c0008b2e6..d88c06f1af 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -85,13 +85,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), -#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD) /* 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), -#endif /* P1020MBG */ +#endif /* TARGET_P1020MBG */ #endif /* RAMBOOT/SPL */ #ifdef CONFIG_SYS_INIT_L2_ADDR |