Merge branch '2021-07-07-remove-non-migrated-platforms'

- Remove a large number of platforms that did not migrate to DM_PCI or DM_USB by 2 years past the migration deadline and do not have a migration imminent.
author: Tom Rini <trini@konsulko.com> 2021-07-07 22:50:41 -0400
committer: Tom Rini <trini@konsulko.com> 2021-07-07 22:50:41 -0400
commit: bfb5bfa3c58adc2ef5dbd1bb95b79b31e0dc221c (patch)
tree: 21753c7f94144a286584c1f631ad9bde89a1a438 /board
parent: 7e58a3a148fb94e9ce09fb48d0ddd75c20ee7df9 (diff)
parent: 123dc510c6e79f0c94718e2e6b5e4074754aa629 (diff)
download: u-boot-bfb5bfa3c58adc2ef5dbd1bb95b79b31e0dc221c.tar.gz
188 files changed, 5 insertions, 11808 deletions
diff --git a/board/Marvell/gplugd/Kconfig b/board/Marvell/gplugd/Kconfig
deleted file mode 100644
index d944816509..0000000000
--- a/board/Marvell/gplugd/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_GPLUGD
-
-config SYS_BOARD
-	default "gplugd"
-
-config SYS_VENDOR
-	default "Marvell"
-
-config SYS_SOC
-	default "armada100"
-
-config SYS_CONFIG_NAME
-	default "gplugd"
-
-endif
diff --git a/board/Marvell/gplugd/MAINTAINERS b/board/Marvell/gplugd/MAINTAINERS
deleted file mode 100644
index 197c6a01dd..0000000000
--- a/board/Marvell/gplugd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GPLUGD BOARD
-M:	Ajay Bhargav <contact@8051projects.net>
-S:	Maintained
-F:	board/Marvell/gplugd/
-F:	include/configs/gplugd.h
-F:	configs/gplugd_defconfig
diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile
deleted file mode 100644
index 6161bf1c84..0000000000
--- a/board/Marvell/gplugd/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2011
-# eInfochips Ltd. <www.einfochips.com>
-# Written-by: Ajay Bhargav <contact@8051projects.net>
-#
-# Based on Aspenite:
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Contributor: Mahavir Jain <mjain@marvell.com>
-
-obj-y	:= gplugd.o
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
deleted file mode 100644
index c6376cdf6a..0000000000
--- a/board/Marvell/gplugd/gplugd.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * Based on Aspenite:
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <mvmfp.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/armada100.h>
-#include <asm/global_data.h>
-#include <asm/gpio.h>
-#include <miiphy.h>
-#include <asm/mach-types.h>
-#include <linux/delay.h>
-
-#ifdef CONFIG_ARMADA100_FEC
-#include <net.h>
-#include <netdev.h>
-#endif /* CONFIG_ARMADA100_FEC */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	u32 mfp_cfg[] = {
-		/* I2C */
-		MFP105_CI2C_SDA,
-		MFP106_CI2C_SCL,
-
-		/* Enable Console on UART3 */
-		MFPO8_UART3_TXD,
-		MFPO9_UART3_RXD,
-
-		/* Ethernet PHY Interface */
-		MFP086_ETH_TXCLK,
-		MFP087_ETH_TXEN,
-		MFP088_ETH_TXDQ3,
-		MFP089_ETH_TXDQ2,
-		MFP090_ETH_TXDQ1,
-		MFP091_ETH_TXDQ0,
-		MFP092_ETH_CRS,
-		MFP093_ETH_COL,
-		MFP094_ETH_RXCLK,
-		MFP095_ETH_RXER,
-		MFP096_ETH_RXDQ3,
-		MFP097_ETH_RXDQ2,
-		MFP098_ETH_RXDQ1,
-		MFP099_ETH_RXDQ0,
-		MFP100_ETH_MDC,
-		MFP101_ETH_MDIO,
-		MFP103_ETH_RXDV,
-
-		/* SSP2 */
-		MFP107_SSP2_RXD,
-		MFP108_SSP2_TXD,
-		MFP110_SSP2_CS,
-		MFP111_SSP2_CLK,
-
-		MFP_EOC		/*End of configuration*/
-	};
-	/* configure MFP's */
-	mfp_config(mfp_cfg);
-	return 0;
-}
-
-int board_init(void)
-{
-	struct armd1apb2_registers *apb2_regs =
-		(struct armd1apb2_registers *)ARMD1_APBC2_BASE;
-
-	/* arch number of Board */
-	gd->bd->bi_arch_number = MACH_TYPE_GPLUGD;
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
-	/* Assert PHY_RST# */
-	gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
-	udelay(10);
-	/* Deassert PHY_RST# */
-	gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
-
-	/* Enable SSP2 clock */
-	writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
-	return 0;
-}
-
-#ifdef CONFIG_ARMADA100_FEC
-int board_eth_init(struct bd_info *bis)
-{
-	struct armd1apmu_registers *apmu_regs =
-		(struct armd1apmu_registers *)ARMD1_APMU_BASE;
-
-	/* Enable clock of ethernet controller */
-	writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
-
-	return armada100_fec_register(ARMD1_FEC_BASE);
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and initialize PHY chip 88E3015 */
-void reset_phy(void)
-{
-	u16 phy_adr;
-	const char *name = "armd-fec0";
-
-	if (miiphy_set_current_dev(name))
-		return;
-
-	/* command to read PHY dev address */
-	if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
-		printf("Err..%s could not read PHY dev address\n", __func__);
-		return;
-	}
-
-	/* Set Ethernet LED in TX blink mode */
-	miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
-	miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
-
-	/* reset the phy */
-	miiphy_reset(name, phy_adr);
-	debug("88E3015 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
-#endif /* CONFIG_ARMADA100_FEC */
diff --git a/board/atmel/at91rm9200ek/Kconfig b/board/atmel/at91rm9200ek/Kconfig
deleted file mode 100644
index 952351dcdb..0000000000
--- a/board/atmel/at91rm9200ek/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_AT91RM9200EK
-
-config SYS_BOARD
-	default "at91rm9200ek"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_CONFIG_NAME
-	default "at91rm9200ek"
-
-endif
diff --git a/board/atmel/at91rm9200ek/MAINTAINERS b/board/atmel/at91rm9200ek/MAINTAINERS
deleted file mode 100644
index b25bc58029..0000000000
--- a/board/atmel/at91rm9200ek/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-AT91RM9200EK BOARD
-M:	Andreas Bießmann <andreas@biessmann.org>
-S:	Maintained
-F:	board/atmel/at91rm9200ek/
-F:	include/configs/at91rm9200ek.h
-F:	configs/at91rm9200ek_defconfig
-F:	configs/at91rm9200ek_ram_defconfig
diff --git a/board/atmel/at91rm9200ek/Makefile b/board/atmel/at91rm9200ek/Makefile
deleted file mode 100644
index 2d5c28082f..0000000000
--- a/board/atmel/at91rm9200ek/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += at91rm9200ek.o
-obj-y += led.o
diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c
deleted file mode 100644
index a314ced5e4..0000000000
--- a/board/atmel/at91rm9200ek/at91rm9200ek.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010 Andreas Bießmann <andreas@biessmann.org>
- *
- * derived from previous work
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/global_data.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_common.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-int board_init(void)
-{
-	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
-
-	/*
-	 * Correct IRDA resistor problem
-	 * Set PA23_TXD in Output
-	 */
-	writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
-
-	/* arch number of AT91RM9200EK-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	at91_seriald_hw_init();
-	return 0;
-}
-
-int dram_init (void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-			CONFIG_SYS_SDRAM_SIZE);
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_AT91EMAC
-int board_eth_init(struct bd_info *bis)
-{
-	return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
-}
-#endif
diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c
deleted file mode 100644
index a6b4d1fb65..0000000000
--- a/board/atmel/at91rm9200ek/led.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2006
- * Atmel Nordic AB <www.atmel.com>
- * Ulf Samuelsson <ulf@atmel.com>
- *
- * (C) Copyright 2010
- * Andreas Bießmann <andreas@biessmann.org>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/at91_pio.h>
-#include <status_led.h>
-
-/* bit mask in PIO port B */
-#define	GREEN_LED	(1<<0)
-#define	YELLOW_LED	(1<<1)
-#define	RED_LED		(1<<2)
-
-void	green_led_on(void)
-{
-	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
-	writel(GREEN_LED, &pio->piob.codr);
-}
-
-void	 yellow_led_on(void)
-{
-	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
-	writel(YELLOW_LED, &pio->piob.codr);
-}
-
-void	 red_led_on(void)
-{
-	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
-	writel(RED_LED, &pio->piob.codr);
-}
-
-void	green_led_off(void)
-{
-	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
-	writel(GREEN_LED, &pio->piob.sodr);
-}
-
-void	yellow_led_off(void)
-{
-	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
-	writel(YELLOW_LED, &pio->piob.sodr);
-}
-
-void	red_led_off(void)
-{
-	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
-	writel(RED_LED, &pio->piob.sodr);
-}
-
-void coloured_LED_init (void)
-{
-	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
-
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-
-	/* Disable peripherals on LEDs */
-	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
-	/* Enable pins as outputs */
-	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
-	/* Turn all LEDs OFF */
-	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
-}
diff --git a/board/cirrus/edb93xx/Kconfig b/board/cirrus/edb93xx/Kconfig
deleted file mode 100644
index c5f4897f8a..0000000000
--- a/board/cirrus/edb93xx/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_EDB93XX
-
-config SYS_BOARD
-	default "edb93xx"
-
-config SYS_VENDOR
-	default "cirrus"
-
-config SYS_SOC
-	default "ep93xx"
-
-config SYS_CONFIG_NAME
-	default "edb93xx"
-
-endif
diff --git a/board/cirrus/edb93xx/MAINTAINERS b/board/cirrus/edb93xx/MAINTAINERS
deleted file mode 100644
index 3bb284335b..0000000000
--- a/board/cirrus/edb93xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-EDB93XX BOARD
-M:	Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
-S:	Maintained
-F:	board/cirrus/edb93xx/
-F:	include/configs/edb93xx.h
-F:	configs/edb9315a_defconfig
diff --git a/board/cirrus/edb93xx/Makefile b/board/cirrus/edb93xx/Makefile
deleted file mode 100644
index 0cf04b13ba..0000000000
--- a/board/cirrus/edb93xx/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2013
-# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
-#
-
-obj-y	:= edb93xx.o
diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c
deleted file mode 100644
index 7a7f62fe88..0000000000
--- a/board/cirrus/edb93xx/edb93xx.c
+++ /dev/null
@@ -1,292 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board initialization for EP93xx
- *
- * Copyright (C) 2013
- * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (C) 2009
- * Matthias Kaehlcke <matthias <at> kaehlcke.net>
- *
- * (C) Copyright 2002 2003
- * Network Audio Technologies, Inc. <www.netaudiotech.com>
- * Adam Bezanson <bezanson <at> netaudiotech.com>
- */
-
-#include <config.h>
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <irq_func.h>
-#include <net.h>
-#include <netdev.h>
-#include <status_led.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/arch/ep93xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * usb_div: 4, nbyp2: 1, pll2_en: 1
- * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
- * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
- */
-#define CLKSET2_VAL	(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
-			24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
-			24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
-			1 << SYSCON_CLKSET_PLL_PS_SHIFT |	\
-			SYSCON_CLKSET2_PLL2_EN |		\
-			SYSCON_CLKSET2_NBYP2 |			\
-			3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
-
-#define SMC_BCR6_VALUE	(2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
-			SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
-			1 << SMC_BCR_MW_SHIFT)
-
-/* delay execution before timers are initialized */
-static inline void early_udelay(uint32_t usecs)
-{
-	/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
-	register uint32_t loops = (usecs * 1000) / 20;
-
-	__asm__ volatile ("1:\n"
-			"subs %0, %1, #1\n"
-			"bne 1b" : "=r" (loops) : "0" (loops));
-}
-
-#ifndef CONFIG_EP93XX_NO_FLASH_CFG
-static void flash_cfg(void)
-{
-	struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
-
-	writel(SMC_BCR6_VALUE, &smc->bcr6);
-}
-#else
-#define flash_cfg()
-#endif
-
-int board_init(void)
-{
-	/*
-	 * Setup PLL2, PPL1 has been set during lowlevel init
-	 */
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-	writel(CLKSET2_VAL, &syscon->clkset2);
-
-	/*
-	 * the user's guide recommends to wait at least 1 ms for PLL2 to
-	 * stabilize
-	 */
-	early_udelay(1000);
-
-	/* Go to Async mode */
-	__asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
-	__asm__ volatile ("orr r0, r0, #0xc0000000");
-	__asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
-
-	icache_enable();
-
-#ifdef USE_920T_MMU
-	dcache_enable();
-#endif
-
-	/* Machine number, as defined in linux/arch/arm/tools/mach-types */
-	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-	/* We have a console */
-	gd->have_console = 1;
-
-	enable_interrupts();
-
-	flash_cfg();
-
-	green_led_on();
-	red_led_off();
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/*
-	 * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
-	 * 14.7456/2 MHz
-	 */
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-	writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
-	return 0;
-}
-
-int board_eth_init(struct bd_info *bd)
-{
-	return ep93xx_eth_initialize(0, MAC_BASE);
-}
-
-static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
-				unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
-{
-	if (dram_bank_cnt == 1) {
-		dram_bank_base[0] = PHYS_SDRAM_1;
-	} else {
-		/* Table lookup for holes in address space. Maximum memory
-		 * for the single SDCS may be up to 256Mb. We start scanning
-		 * banks from 1Mb, so it could be up to 128 banks theoretically.
-		 * We need at maximum 7 bits for the loockup, 8 slots is
-		 * enough for the worst case.
-		 */
-		unsigned tbl[8];
-		unsigned i = dram_bank_cnt / 2;
-		unsigned j = 0x00100000; /* 1 Mb */
-		unsigned *ptbl = tbl;
-		do {
-			while (!(dram_addr_mask & j)) {
-				j <<= 1;
-			}
-			*ptbl++ = j;
-			j <<= 1;
-			i >>= 1;
-		} while (i != 0);
-
-		for (i = dram_bank_cnt, j = 0;
-		     (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
-			unsigned addr = PHYS_SDRAM_1;
-			unsigned k;
-			unsigned bit;
-
-			for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
-				if (bit & j)
-					addr |= tbl[k];
-			}
-
-			dram_bank_base[j] = addr;
-		}
-	}
-}
-
-/* called in board_init_f (before relocation) */
-static unsigned dram_init_banksize_int(int print)
-{
-	/*
-	 * Collect information of banks that has been filled during lowlevel
-	 * initialization
-	 */
-	unsigned i;
-	unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
-	unsigned dram_total = 0;
-	unsigned dram_bank_size = *(unsigned *)
-				  (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
-	unsigned dram_addr_mask = *(unsigned *)
-				  (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
-	unsigned dram_bank_cnt = *(unsigned *)
-				 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
-
-	dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
-
-	for (i = 0; i < dram_bank_cnt; i++) {
-		gd->bd->bi_dram[i].start = dram_bank_base[i];
-		gd->bd->bi_dram[i].size = dram_bank_size;
-		dram_total += dram_bank_size;
-	}
-	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = 0;
-		gd->bd->bi_dram[i].size = 0;
-	}
-
-	if (print) {
-		printf("DRAM mask: %08x\n", dram_addr_mask);
-		printf("DRAM total %u banks:\n", dram_bank_cnt);
-		printf("bank          base-address          size\n");
-
-		if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
-			printf("WARNING! UBoot was configured for %u banks,\n"
-				"but %u has been found. "
-				"Supressing extra memory banks\n",
-				 CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
-			dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
-		}
-
-		for (i = 0; i < dram_bank_cnt; i++) {
-			printf("  %u             %08x            %08x\n",
-			       i, dram_bank_base[i], dram_bank_size);
-		}
-		printf("  ------------------------------------------\n"
-			"Total                              %9d\n\n",
-			dram_total);
-	}
-
-	return dram_total;
-}
-
-int dram_init_banksize(void)
-{
-	dram_init_banksize_int(0);
-
-	return 0;
-}
-
-/* called in board_init_f (before relocation) */
-int dram_init(void)
-{
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-	unsigned sec_id = readl(SECURITY_EXTENSIONID);
-	unsigned chip_id = readl(&syscon->chipid);
-
-	printf("CPU: Cirrus Logic ");
-	switch (sec_id & 0x000001FE) {
-	case 0x00000008:
-		printf("EP9301");
-		break;
-	case 0x00000004:
-		printf("EP9307");
-		break;
-	case 0x00000002:
-		printf("EP931x");
-		break;
-	case 0x00000000:
-		printf("EP9315");
-		break;
-	default:
-		printf("<unknown>");
-		break;
-	}
-
-	printf(" - Rev. ");
-	switch (chip_id & 0xF0000000) {
-	case 0x00000000:
-		printf("A");
-		break;
-	case 0x10000000:
-		printf("B");
-		break;
-	case 0x20000000:
-		printf("C");
-		break;
-	case 0x30000000:
-		printf("D0");
-		break;
-	case 0x40000000:
-		printf("D1");
-		break;
-	case 0x50000000:
-		printf("E0");
-		break;
-	case 0x60000000:
-		printf("E1");
-		break;
-	case 0x70000000:
-		printf("E2");
-		break;
-	default:
-		printf("?");
-		break;
-	}
-	printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
-
-	gd->ram_size = dram_init_banksize_int(1);
-	return 0;
-}
diff --git a/board/cirrus/edb93xx/u-boot.lds b/board/cirrus/edb93xx/u-boot.lds
deleted file mode 100644
index db45c00e1a..0000000000
--- a/board/cirrus/edb93xx/u-boot.lds
+++ /dev/null
@@ -1,115 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * Copyright (C) 2013
- * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text : {
-		*(.__image_copy_start)
-		*(.vectors)
-		arch/arm/cpu/arm920t/start.o (.text*)
-		. = 0x1000;
-
-		LONG(0x53555243)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	.end :
-	{
-		*(.__end)
-	}
-
-	_image_binary_end = .;
-
-	/*
-	 * Deprecated: this MMU section is used by pxa at present but
-	 * should not be used by new boards/CPUs.
-	 */
-	. = ALIGN(4096);
-	.mmutable : {
-		*(.mmutable)
-	}
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	.dynsym _image_binary_end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu.hash : { *(.gnu.hash) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-	.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
-}
diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig
deleted file mode 100644
index ef2af40f7e..0000000000
--- a/board/esd/vme8349/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_VME8349
-
-config SYS_BOARD
-	default "vme8349"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "vme8349"
-
-endif
-
-if TARGET_CADDY2
-
-config SYS_BOARD
-	default "vme8349"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "caddy2"
-
-endif
diff --git a/board/esd/vme8349/MAINTAINERS b/board/esd/vme8349/MAINTAINERS
deleted file mode 100644
index a88ba13c30..0000000000
--- a/board/esd/vme8349/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-VME8349 BOARD
-M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S:	Maintained
-F:	board/esd/vme8349/
-F:	include/configs/vme8349.h
-F:	configs/caddy2_defconfig
-F:	configs/vme8349_defconfig
diff --git a/board/esd/vme8349/Makefile b/board/esd/vme8349/Makefile
deleted file mode 100644
index 850c16ba63..0000000000
--- a/board/esd/vme8349/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (c) 2009 esd gmbh hannover germany.
-
-obj-y += vme8349.o caddy.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/esd/vme8349/caddy.c b/board/esd/vme8349/caddy.c
deleted file mode 100644
index ba91f4b3c8..0000000000
--- a/board/esd/vme8349/caddy.c
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-
-#include "caddy.h"
-
-static struct caddy_interface *caddy_interface;
-
-void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
-{
-	struct caddy_answer *answer;
-	uint32_t ptr;
-
-	answer = &caddy_interface->answer[caddy_interface->answer_in];
-	memset((void *)answer, 0, sizeof(struct caddy_answer));
-	answer->answer = cmd->cmd;
-	answer->issue = cmd->issue;
-	answer->status = status;
-	memcpy(answer->par, result, 5 * sizeof(result[0]));
-	ptr = caddy_interface->answer_in + 1;
-	ptr = ptr & (ANSWER_SIZE - 1);
-	if (ptr != caddy_interface->answer_out)
-		caddy_interface->answer_in = ptr;
-}
-
-int do_caddy(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
-	unsigned long base_addr;
-	uint32_t ptr;
-	struct caddy_cmd *caddy_cmd;
-	uint32_t result[5];
-	uint16_t data16;
-	uint8_t data8;
-	uint32_t status;
-	pci_dev_t dev;
-	void *pci_ptr;
-
-	if (argc < 2) {
-		puts("Missing parameter\n");
-		return 1;
-	}
-
-	base_addr = simple_strtoul(argv[1], NULL, 16);
-	caddy_interface = (struct caddy_interface *) base_addr;
-
-	memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
-	memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
-
-	while (ctrlc() == 0) {
-		if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
-			memset(result, 0, 5 * sizeof(result[0]));
-			status = 0;
-			caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
-			pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
-				(caddy_cmd->addr & 0x001fffff);
-
-			switch (caddy_cmd->cmd) {
-			case CADDY_CMD_IO_READ_8:
-				result[0] = in_8(pci_ptr);
-				break;
-
-			case CADDY_CMD_IO_READ_16:
-				result[0] = in_be16(pci_ptr);
-				break;
-
-			case CADDY_CMD_IO_READ_32:
-				result[0] = in_be32(pci_ptr);
-				break;
-
-			case CADDY_CMD_IO_WRITE_8:
-				data8 = caddy_cmd->par[0] & 0x000000ff;
-				out_8(pci_ptr, data8);
-				break;
-
-			case CADDY_CMD_IO_WRITE_16:
-				data16 = caddy_cmd->par[0] & 0x0000ffff;
-				out_be16(pci_ptr, data16);
-				break;
-
-			case CADDY_CMD_IO_WRITE_32:
-				out_be32(pci_ptr, caddy_cmd->par[0]);
-				break;
-
-			case CADDY_CMD_CONFIG_READ_8:
-				dev = PCI_BDF(caddy_cmd->par[0],
-					      caddy_cmd->par[1],
-					      caddy_cmd->par[2]);
-				status = pci_read_config_byte(dev,
-							      caddy_cmd->addr,
-							      &data8);
-				result[0] = data8;
-				break;
-
-			case CADDY_CMD_CONFIG_READ_16:
-				dev = PCI_BDF(caddy_cmd->par[0],
-					      caddy_cmd->par[1],
-					      caddy_cmd->par[2]);
-				status = pci_read_config_word(dev,
-							      caddy_cmd->addr,
-							      &data16);
-				result[0] = data16;
-				break;
-
-			case CADDY_CMD_CONFIG_READ_32:
-				dev = PCI_BDF(caddy_cmd->par[0],
-					      caddy_cmd->par[1],
-					      caddy_cmd->par[2]);
-				status = pci_read_config_dword(dev,
-							       caddy_cmd->addr,
-							       &result[0]);
-				break;
-
-			case CADDY_CMD_CONFIG_WRITE_8:
-				dev = PCI_BDF(caddy_cmd->par[0],
-					      caddy_cmd->par[1],
-					      caddy_cmd->par[2]);
-				data8 = caddy_cmd->par[3] & 0x000000ff;
-				status = pci_write_config_byte(dev,
-							       caddy_cmd->addr,
-							       data8);
-				break;
-
-			case CADDY_CMD_CONFIG_WRITE_16:
-				dev = PCI_BDF(caddy_cmd->par[0],
-					      caddy_cmd->par[1],
-					      caddy_cmd->par[2]);
-				data16 = caddy_cmd->par[3] & 0x0000ffff;
-				status = pci_write_config_word(dev,
-							       caddy_cmd->addr,
-							       data16);
-				break;
-
-			case CADDY_CMD_CONFIG_WRITE_32:
-				dev = PCI_BDF(caddy_cmd->par[0],
-					      caddy_cmd->par[1],
-					      caddy_cmd->par[2]);
-				status = pci_write_config_dword(dev,
-								caddy_cmd->addr,
-								caddy_cmd->par[3]);
-				break;
-
-			default:
-				status = 0xffffffff;
-				break;
-			}
-
-			generate_answer(caddy_cmd, status, &result[0]);
-
-			ptr = caddy_interface->cmd_out + 1;
-			ptr = ptr & (CMD_SIZE - 1);
-			caddy_interface->cmd_out = ptr;
-		}
-
-		caddy_interface->heartbeat++;
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	caddy,	2,	0,	do_caddy,
-	"Start Caddy server.",
-	"Start Caddy server with Data structure a given addr\n"
-	);
diff --git a/board/esd/vme8349/caddy.h b/board/esd/vme8349/caddy.h
deleted file mode 100644
index 8e3033ba20..0000000000
--- a/board/esd/vme8349/caddy.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- */
-
-#ifndef __CADDY_H__
-#define __CADDY_H__
-
-#define CMD_SIZE	1024
-#define ANSWER_SIZE	1024
-#define CADDY_MAGIC	"esd vme8349 V1.0"
-
-enum caddy_cmds {
-	CADDY_CMD_IO_READ_8,
-	CADDY_CMD_IO_READ_16,
-	CADDY_CMD_IO_READ_32,
-	CADDY_CMD_IO_WRITE_8,
-	CADDY_CMD_IO_WRITE_16,
-	CADDY_CMD_IO_WRITE_32,
-	CADDY_CMD_CONFIG_READ_8,
-	CADDY_CMD_CONFIG_READ_16,
-	CADDY_CMD_CONFIG_READ_32,
-	CADDY_CMD_CONFIG_WRITE_8,
-	CADDY_CMD_CONFIG_WRITE_16,
-	CADDY_CMD_CONFIG_WRITE_32,
-};
-
-struct caddy_cmd {
-	uint32_t cmd;
-	uint32_t issue;
-	uint32_t addr;
-	uint32_t par[5];
-};
-
-struct caddy_answer {
-	uint32_t answer;
-	uint32_t issue;
-	uint32_t status;
-	uint32_t par[5];
-};
-
-struct caddy_interface {
-	uint8_t  magic[16];
-	uint32_t cmd_in;
-	uint32_t cmd_out;
-	uint32_t heartbeat;
-	uint32_t reserved1;
-	struct caddy_cmd cmd[CMD_SIZE];
-	uint32_t answer_in;
-	uint32_t answer_out;
-	uint32_t reserved2;
-	uint32_t reserved3;
-	struct caddy_answer answer[CMD_SIZE];
-};
-
-#endif /* of __CADDY_H__ */
diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c
deleted file mode 100644
index bf51d39b67..0000000000
--- a/board/esd/vme8349/pci.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * pci.c -- esd VME8349 PCI board support.
- * Copyright (c) 2006 Wind River Systems, Inc.
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * Based on MPC8349 PCI support but w/o PIB related code.
- */
-
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-#include "vme8349pin.h"
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-/*
- * pci_init_board()
- *
- * NOTICE: PCI2 is not supported. There is only one
- * physical PCI slot on the board.
- *
- */
-void
-pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci1_regions };
-	u8 reg8;
-	int monarch = 0;
-
-	i2c_set_bus_num(1);
-	/* Read the PCI_M66EN jumper setting */
-	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, 1) == 0) ||
-	    (i2c_read(0x38                     , 0, 0, &reg8, 1) == 0)) {
-		if (reg8 & 0x40) {
-			clk->occr = 0xff000000;	/* 66 MHz PCI */
-			printf("PCI:   66MHz\n");
-		} else {
-			clk->occr = 0xffff0003;	/* 33 MHz PCI */
-			printf("PCI:   33MHz\n");
-		}
-		if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
-			monarch = 1;
-	} else {
-		clk->occr = 0xffff0003;	/* 33 MHz PCI */
-		printf("PCI:   33MHz (I2C read failed)\n");
-	}
-	udelay(2000);
-
-	/*
-	 * Assert/deassert VME reset
-	 */
-	clrsetbits_be32(&immr->gpio[1].dat,
-			GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
-			GPIO2_VME_RESET_N  | GPIO2_L_RESET_EN_N);
-	setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
-		     GPIO2_TSI_POWERUP_RESET_N |
-		     GPIO2_VME_RESET_N |
-		     GPIO2_L_RESET_EN_N);
-	clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
-	udelay(200);
-	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
-	udelay(200);
-	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
-	udelay(600000);
-	clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	udelay(2000);
-
-	if (monarch == 0) {
-		mpc83xx_pci_init(1, reg);
-	} else {
-		/*
-		 * Release PCI RST Output signal
-		 */
-		out_be32(&immr->pci_ctrl[0].gcr, 0);
-		udelay(2000);
-		out_be32(&immr->pci_ctrl[0].gcr, 1);
-	}
-}
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
deleted file mode 100644
index d388fc6d49..0000000000
--- a/board/esd/vme8349/vme8349.c
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * vme8349.c -- esd VME8349 board support
- *
- * Copyright (c) 2008-2009 esd gmbh.
- *
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <asm/mpc8349_pci.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <spd.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void ddr_enable_ecc(unsigned int dram_size);
-
-int dram_init(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -ENXIO;
-
-	/* DDR SDRAM - Main memory */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-
-	msize = spd_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
-	/* Now check memory size (after ECC is initialized) */
-	msize = get_ram_size(0, msize);
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	gd->ram_size = msize * 1024 * 1024;
-
-	return 0;
-}
-
-int checkboard(void)
-{
-#ifdef CONFIG_TARGET_CADDY2
-	puts("Board: esd VME-CADDY/2\n");
-#else
-	puts("Board: esd VME-CPU/8349\n");
-#endif
-
-	return 0;
-}
-
-#ifdef CONFIG_TARGET_CADDY2
-int board_eth_init(struct bd_info *bis)
-{
-	return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
-
-int misc_init_r()
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
-
-	return 0;
-}
-
-/*
- * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
- * and VME-CADDY/2) have different SDRAM configurations.
- */
-#ifdef CONFIG_TARGET_CADDY2
-#define SMALL_RAM	0xff
-#define LARGE_RAM	0x00
-#else
-#define SMALL_RAM	0x00
-#define LARGE_RAM	0xff
-#endif
-
-#define SPD_VAL(a, b)	(((a) & SMALL_RAM) | ((b) & LARGE_RAM))
-
-static spd_eeprom_t default_spd_eeprom = {
-	SPD_VAL(0x80, 0x80),	/* 00 use 128 Bytes */
-	SPD_VAL(0x07, 0x07),	/* 01 use 128 Bytes */
-	SPD_MEMTYPE_DDR2,	/* 02 type is DDR2 */
-	SPD_VAL(0x0d, 0x0d),	/* 03 rows: 13 */
-	SPD_VAL(0x09, 0x0a),	/* 04 cols:  9 / 10 */
-	SPD_VAL(0x00, 0x00),	/* 05 */
-	SPD_VAL(0x40, 0x40),	/* 06 */
-	SPD_VAL(0x00, 0x00),	/* 07 */
-	SPD_VAL(0x05, 0x05),	/* 08 */
-	SPD_VAL(0x30, 0x30),	/* 09 */
-	SPD_VAL(0x45, 0x45),	/* 10 */
-	SPD_VAL(0x02, 0x02),	/* 11 ecc used */
-	SPD_VAL(0x82, 0x82),	/* 12 */
-	SPD_VAL(0x10, 0x10),	/* 13 */
-	SPD_VAL(0x08, 0x08),	/* 14 */
-	SPD_VAL(0x00, 0x00),	/* 15 */
-	SPD_VAL(0x0c, 0x0c),	/* 16 */
-	SPD_VAL(0x04, 0x08),	/* 17 banks: 4 / 8 */
-	SPD_VAL(0x38, 0x38),	/* 18 */
-	SPD_VAL(0x00, 0x00),	/* 19 */
-	SPD_VAL(0x02, 0x02),	/* 20 */
-	SPD_VAL(0x00, 0x00),	/* 21 */
-	SPD_VAL(0x03, 0x03),	/* 22 */
-	SPD_VAL(0x3d, 0x3d),	/* 23 */
-	SPD_VAL(0x45, 0x45),	/* 24 */
-	SPD_VAL(0x50, 0x50),	/* 25 */
-	SPD_VAL(0x45, 0x45),	/* 26 */
-	SPD_VAL(0x3c, 0x3c),	/* 27 */
-	SPD_VAL(0x28, 0x28),	/* 28 */
-	SPD_VAL(0x3c, 0x3c),	/* 29 */
-	SPD_VAL(0x2d, 0x2d),	/* 30 */
-	SPD_VAL(0x20, 0x80),	/* 31 */
-	SPD_VAL(0x20, 0x20),	/* 32 */
-	SPD_VAL(0x27, 0x27),	/* 33 */
-	SPD_VAL(0x10, 0x10),	/* 34 */
-	SPD_VAL(0x17, 0x17),	/* 35 */
-	SPD_VAL(0x3c, 0x3c),	/* 36 */
-	SPD_VAL(0x1e, 0x1e),	/* 37 */
-	SPD_VAL(0x1e, 0x1e),	/* 38 */
-	SPD_VAL(0x00, 0x00),	/* 39 */
-	SPD_VAL(0x00, 0x06),	/* 40 */
-	SPD_VAL(0x37, 0x37),	/* 41 */
-	SPD_VAL(0x4b, 0x7f),	/* 42 */
-	SPD_VAL(0x80, 0x80),	/* 43 */
-	SPD_VAL(0x18, 0x18),	/* 44 */
-	SPD_VAL(0x22, 0x22),	/* 45 */
-	SPD_VAL(0x00, 0x00),	/* 46 */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-	SPD_VAL(0x10, 0x10),	/* 62 */
-	SPD_VAL(0x7e, 0x1d),	/* 63 */
-	{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
-	SPD_VAL(0x00, 0x00),	/* 72 */
-#ifdef CONFIG_TARGET_CADDY2
-	{ "vme-caddy/2 ram   " }
-#else
-	{ "vme-cpu/2 ram     " }
-#endif
-};
-
-int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-	int old_bus = i2c_get_bus_num();
-	unsigned int l, sum;
-	int valid = 0;
-
-	i2c_set_bus_num(0);
-
-	if (i2c_read(chip, addr, alen, buffer, len) == 0)
-		if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
-			sum = 0;
-			for (l = 0; l < 63; l++)
-				sum = (sum + buffer[l]) & 0xff;
-			if (sum == buffer[63])
-				valid = 1;
-			else
-				printf("Invalid checksum in EEPROM %02x %02x\n",
-				       sum, buffer[63]);
-		}
-
-	if (valid == 0) {
-		memcpy(buffer, (void *)&default_spd_eeprom, len);
-		sum = 0;
-		for (l = 0; l < 63; l++)
-			sum = (sum + buffer[l]) & 0xff;
-		if (sum != buffer[63])
-			printf("Invalid checksum in FLASH %02x %02x\n",
-			       sum, buffer[63]);
-		buffer[63] = sum;
-	}
-
-	i2c_set_bus_num(old_bus);
-
-	return 0;
-}
diff --git a/board/esd/vme8349/vme8349pin.h b/board/esd/vme8349/vme8349pin.h
deleted file mode 100644
index 9ae9c7beca..0000000000
--- a/board/esd/vme8349/vme8349pin.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- */
-
-#ifndef __VME8349PIN_H__
-#define __VME8349PIN_H__
-
-#define GPIO2_V_SCON		0x80000000 /* In:  from tsi148 1: is syscon */
-#define GPIO2_VME_RESET_N	0x20000000 /* Out: to tsi148                */
-#define GPIO2_TSI_PLL_RESET_N	0x08000000 /* Out: to tsi148                */
-#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148              */
-#define GPIO2_L_RESET_EN_N	0x00100000 /* Out: 0:vme can assert cpu lrst*/
-
-#endif /* of ifndef __VME8349PIN_H__ */
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 114b7ba8f9..7862a791ac 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -43,9 +43,7 @@ endif
 
 obj-$(CONFIG_FSL_DCU_SII9022A)    += dcu_sii9022a.o
 
-obj-$(CONFIG_TARGET_MPC8541CDS)	+= cds_pci_ft.o
 obj-$(CONFIG_TARGET_MPC8548CDS)	+= cds_pci_ft.o
-obj-$(CONFIG_TARGET_MPC8555CDS)	+= cds_pci_ft.o
 
 obj-$(CONFIG_TARGET_MPC8536DS)	+= ics307_clk.o
 obj-$(CONFIG_TARGET_P1022DS)		+= ics307_clk.o
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index 596cd0018c..162c8a954f 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -36,11 +36,7 @@ int pib_init(void)
 	i2c_write(0x26, 0x6, 1, &val8, 1);
 	val8 = 0x34;
 	i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(CONFIG_TARGET_MPC832XEMDS)
-	val8 = 0xf9;            /* PMC2, PMC3 slot to PCI bus */
-#else
 	val8 = 0xf3;		/* PMC1, PMC2, PMC3 slot to PCI bus */
-#endif
 	i2c_write(0x26, 0x2, 1, &val8, 1);
 	val8 = 0xff;
 	i2c_write(0x26, 0x3, 1, &val8, 1);
@@ -55,34 +51,9 @@ int pib_init(void)
 
 	eieio();
 
-#if defined(CONFIG_TARGET_MPC832XEMDS)
-	printf("PCI 32bit bus on PMC2 &PMC3\n");
-#else
 	printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
 #endif
-#endif
-
-#if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_TARGET_MPC832XEMDS)
-	val8 = 0;
-	i2c_write(0x26, 0x7, 1, &val8, 1);
-	val8 = 0xf7;
-	i2c_write(0x26, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x21, 0x6, 1, &val8, 1);
-	i2c_write(0x21, 0x7, 1, &val8, 1);
-
-	val8 = 0xdf;
-	i2c_write(0x21, 0x2, 1, &val8, 1);
-	val8 = 0xef;
-	i2c_write(0x21, 0x3, 1, &val8, 1);
 
-	eieio();
-
-	printf("QOC3 ATM card on PMC1\n");
-#endif
-#endif
 	/* Reset to original I2C bus */
 	i2c_set_bus_num(orig_i2c_bus);
 	return 0;
diff --git a/board/freescale/m547xevb/Kconfig b/board/freescale/m547xevb/Kconfig
deleted file mode 100644
index 8cfe20ab8d..0000000000
--- a/board/freescale/m547xevb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M5475EVB
-
-config SYS_CPU
-	default "mcf547x_8x"
-
-config SYS_BOARD
-	default "m547xevb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "M5475EVB"
-
-endif
diff --git a/board/freescale/m547xevb/MAINTAINERS b/board/freescale/m547xevb/MAINTAINERS
deleted file mode 100644
index 0d821eb011..0000000000
--- a/board/freescale/m547xevb/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-M547XEVB BOARD
-M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
-S:	Maintained
-F:	board/freescale/m547xevb/
-F:	include/configs/M5475EVB.h
-F:	configs/M5475AFE_defconfig
-F:	configs/M5475BFE_defconfig
-F:	configs/M5475CFE_defconfig
-F:	configs/M5475DFE_defconfig
-F:	configs/M5475EFE_defconfig
-F:	configs/M5475FFE_defconfig
-F:	configs/M5475GFE_defconfig
diff --git a/board/freescale/m547xevb/Makefile b/board/freescale/m547xevb/Makefile
deleted file mode 100644
index 29fe9dad77..0000000000
--- a/board/freescale/m547xevb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	= m547xevb.o
diff --git a/board/freescale/m547xevb/README b/board/freescale/m547xevb/README
deleted file mode 100644
index 6b4fbe5c25..0000000000
--- a/board/freescale/m547xevb/README
+++ /dev/null
@@ -1,271 +0,0 @@
-Freescale MCF5475EVB ColdFire Development Board
-================================================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created Jan 08, 2008
-===========================================
-
-
-Changed files:
-==============
-
-- board/freescale/m547xevb/m547xevb.c	Dram setup, IDE pre init, and PCI init
-- board/freescale/m547xevb/mii.c	MII init
-- board/freescale/m547xevb/Makefile	Makefile
-- board/freescale/m547xevb/config.mk	config make
-- board/freescale/m547xevb/u-boot.lds	Linker description
-
-- arch/m68k/cpu/mcf547x_8x/cpu.c			cpu specific code
-- arch/m68k/cpu/mcf547x_8x/cpu_init.c		Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
-- arch/m68k/cpu/mcf547x_8x/interrupts.c		cpu specific interrupt support
-- arch/m68k/cpu/mcf547x_8x/slicetimer.c		Timer support
-- arch/m68k/cpu/mcf547x_8x/speed.c		system, pci, flexbus, and cpu clock
-- arch/m68k/cpu/mcf547x_8x/Makefile		Makefile
-- arch/m68k/cpu/mcf547x_8x/config.mk		config make
-- arch/m68k/cpu/mcf547x_8x/start.S		start up assembly code
-
-- board/freescale/m547xevb/README	This readme file
-
-- drivers/dma/MCD_dmaApi.c		DMA API functions
-- drivers/dma/MCD_tasks.c		DMA Tasks
-- drivers/dma/MCD_tasksInit.c		DMA Tasks Init
-- drivers/net/fsl_mcdmafec.c		ColdFire common DMA FEC driver
-- drivers/serial/mcfuart.c		ColdFire common UART driver
-
-- include/MCD_dma.h			DMA header file
-- include/MCD_progCheck.h		DMA header file
-- include/MCD_tasksInit.h		DMA header file
-- include/asm-m68k/bitops.h		Bit operation function export
-- include/asm-m68k/byteorder.h		Byte order functions
-- include/asm-m68k/errno.h		Error Number definition
-- include/asm-m68k/fec.h		FEC structure and definition
-- include/asm-m68k/fsl_i2c.h		I2C structure and definition
-- include/asm-m68k/fsl_mcddmafec.h	DMA FEC structure and definition
-- include/asm-m68k/global_data.h	Global data structure
-- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
-- include/asm-m68k/immap_547x_8x.h	mcf547x_8x specific header file
-- include/asm-m68k/io.h			io functions
-- include/asm-m68k/m547x_8x.h		mcf547x_8x specific header file
-- include/asm-m68k/posix_types.h	Posix
-- include/asm-m68k/processor.h		header file
-- include/asm-m68k/ptrace.h		Exception structure
-- include/asm-m68k/rtc.h		Realtime clock header file
-- include/asm-m68k/string.h		String function export
-- include/asm-m68k/timer.h		Timer structure and definition
-- include/asm-m68k/types.h		Data types definition
-- include/asm-m68k/uart.h		Uart structure and definition
-- include/asm-m68k/u-boot.h		U-Boot structure
-
-- include/configs/M5475EVB.h		Board specific configuration file
-
-- arch/m68k/lib/board.c			board init function
-- arch/m68k/lib/cache.c
-- arch/m68k/lib/interrupts			Coldfire common interrupt functions
-- arch/m68k/lib/m68k_linux.c
-- arch/m68k/lib/traps.c			Exception init code
-
-1 MCF547x specific Options/Settings
-====================================
-1.1 pre-loader is no longer suppoer in thie coldfire family
-
-1.2 Configuration settings for M5475EVB Development Board
-CONFIG_MCF547x_8x	-- define for all MCF547x_8x CPUs
-CONFIG_M547x		-- define for all Freescale MCF547x CPUs
-CONFIG_M5475		-- define for M5475EVB board
-
-CONFIG_MCFUART		-- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
-CONFIG_BAUDRATE		-- define UART baudrate
-
-CONFIG_FSLDMAFEC	-- define to use common dma FEC driver
-CONFIG_MII		-- enable to use MII driver
-CONFIG_CF_DOMII		-- enable to use MII feature in cmd_mii.c
-CONFIG_SYS_DISCOVER_PHY	-- enable PHY discovery
-CONFIG_SYS_RX_ETH_BUFFER	-- Set FEC Receive buffer
-CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
-CONFIG_SYS_FEC0_PINMUX		-- Set FEC0 Pin configuration
-CONFIG_SYS_FEC1_PINMUX		-- Set FEC1 Pin configuration
-CONFIG_SYS_FEC0_MIIBASE	-- Set FEC0 MII base register
-CONFIG_SYS_FEC1_MIIBASE	-- Set FEC0 MII base register
-MCFFEC_TOUT_LOOP	-- set FEC timeout loop
-CONFIG_HAS_ETH1		-- define to enable second FEC in U-Boot
-
-CONFIG_CMD_USB		-- enable USB commands
-CONFIG_USB_OHCI_NEW	-- enable USB OHCI driver
-CONFIG_USB_STORAGE	-- enable USB Storage device
-CONFIG_DOS_PARTITION	-- enable DOS read/write
-
-CONFIG_SLTTMR		-- define to use SLT timer
-
-CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
-CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
-CONFIG_SYS_I2C_SPEED		-- define for I2C speed
-CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
-CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
-CONFIG_SYS_IMMR		-- define for MBAR offset
-
-CONFIG_PCI		-- define for PCI support
-CONFIG_PCI_PNP		-- define for Plug n play support
-CONFIG_SKIPPCI_HOSTBRIDGE	-- SKIP PCI Host bridge
-CONFIG_SYS_PCI_MEM_BUS		-- PCI memory logical offset
-CONFIG_SYS_PCI_MEM_PHYS	-- PCI memory physical offset
-CONFIG_SYS_PCI_MEM_SIZE	-- PCI memory size
-CONFIG_SYS_PCI_IO_BUS		-- PCI IO logical offset
-CONFIG_SYS_PCI_IO_PHYS		-- PCI IO physical offset
-CONFIG_SYS_PCI_IO_SIZE		-- PCI IO size
-CONFIG_SYS_PCI_CFG_BUS		-- PCI Configuration logical offset
-CONFIG_SYS_PCI_CFG_PHYS	-- PCI Configuration physical offset
-CONFIG_SYS_PCI_CFG_SIZE	-- PCI Configuration size
-
-CONFIG_SYS_MBAR		-- define MBAR offset
-
-CONFIG_MONITOR_IS_IN_RAM -- Not support
-
-CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF547x internal SRAM
-
-CONFIG_SYS_CSn_BASE	-- defines the Chip Select Base register
-CONFIG_SYS_CSn_MASK	-- defines the Chip Select Mask register
-CONFIG_SYS_CSn_CTRL	-- defines the Chip Select Control register
-
-CONFIG_SYS_SDRAM_BASE	-- defines the DRAM Base
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. System memory map:
-	Flash:		0xFF800000-0xFFFFFFFF (8MB)
-	DDR:		0x00000000-0x3FFFFFFF (1024MB)
-	SRAM:		0xF2000000-0xF2000FFF (4KB)
-	PCI:		0x70000000-0x8FFFFFFF (512MB)
-	IP:		0xF0000000-0xFFFFFFFF (256MB)
-
-3. COMPILATION
-==============
-3.1	To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux
-	version) from codesourcery.com was used. Download it from:
-	http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
-
-3.2 Compilation
-   export CROSS_COMPILE=cross-compile-prefix
-   cd u-boot-1.x.x
-   make distclean
-   make M5475AFE_config, or	- boot 2MB, RAM 64MB
-   make M5475BFE_config, or	- boot 2MB, code 16MB, RAM 64MB
-   make M5475CFE_config, or	- boot 2MB, code 16MB, Video, USB, RAM 64MB
-   make M5475DFE_config, or	- boot 2MB, USB, RAM 64MB
-   make M5475EFE_config, or	- boot 2MB, Video, USB, RAM 64MB
-   make M5475FFE_config, or	- boot 2MB, code 32MB, Video, USB, RAM 128MB
-   make M5475GFE_config, or	- boot 2MB, RAM 64MB
-   make
-
-5. SCREEN DUMP
-==============
-5.1
-
-U-Boot 1.3.1 (Jan  8 2008 - 12:47:44)
-
-CPU:   Freescale MCF5475
-       CPU CLK 266 Mhz BUS CLK 133 Mhz
-Board: Freescale FireEngine 5475 EVB
-I2C:   ready
-DRAM:  64 MB
-FLASH: 18 MB
-In:    serial
-Out:   serial
-Err:   serial
-Net:   FEC0, FEC1
--> pri
-bootdelay=1
-baudrate=115200
-ethaddr=00:e0:0c:bc:e5:60
-eth1addr=00:e0:0c:bc:e5:61
-ipaddr=192.162.1.2
-serverip=192.162.1.1
-gatewayip=192.162.1.1
-netmask=255.255.255.0
-hostname=M547xEVB
-netdev=eth0
-loadaddr=10000
-u-boot=u-boot.bin
-load=tftp ${loadaddr) ${u-boot}
-upd=run load; run prog
-prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save
-stdin=serial
-stdout=serial
-stderr=serial
-ethact=FEC0
-mem=65024k
-
-Environment size: 433/8188 bytes
--> bdin
-memstart    = 0x00000000
-memsize     = 0x04000000
-flashstart  = 0xFF800000
-flashsize   = 0x01200000
-flashoffset = 0x00000000
-sramstart   = 0xF2000000
-sramsize    = 0x00001000
-mbar	    = 0xF0000000
-busfreq     = 133.333 MHz
-pcifreq     =	   0 MHz
-ethaddr     = 00:E0:0C:BC:E5:60
-eth1addr    = 00:E0:0C:BC:E5:61
-ip_addr     = 192.162.1.2
-baudrate    = 115200 bps
--> ?
-?	- alias for 'help'
-base	- print or set address offset
-bdinfo	- print Board Info structure
-boot	- boot default, i.e., run 'bootcmd'
-bootd	- boot default, i.e., run 'bootcmd'
-bootelf - Boot from an ELF image in memory
-bootm	- boot application image from memory
-bootp	- boot image via network using BootP/TFTP protocol
-bootvx	- Boot vxWorks from an ELF image
-cmp	- memory compare
-coninfo - print console devices and information
-cp	- memory copy
-crc32	- checksum calculation
-dcache	- enable or disable data cache
-echo	- echo args to console
-erase	- erase FLASH memory
-flinfo	- print FLASH memory information
-go	- start application at address 'addr'
-help	- print online help
-i2c	- I2C sub-system
-icache	- enable or disable instruction cache
-iminfo	- print header information for application image
-imls	- list all images found in flash
-itest	- return true/false on integer compare
-loadb	- load binary file over serial line (kermit mode)
-loads	- load S-Record file over serial line
-loady	- load binary file over serial line (ymodem mode)
-loop	- infinite loop on address range
-md	- memory display
-mii	- MII utility commands
-mm	- memory modify (auto-incrementing)
-mtest	- simple RAM test
-mw	- memory write (fill)
-nfs	- boot image via network using NFS protocol
-nm	- memory modify (constant address)
-pci	- list and access PCI Configuration Space
-ping	- send ICMP ECHO_REQUEST to network host
-printenv- print environment variables
-protect - enable or disable FLASH write protection
-rarpboot- boot image via network using RARP/TFTP protocol
-reset	- Perform RESET of the CPU
-run	- run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv	- set environment variables
-sleep	- delay execution for some time
-source	- run script from memory
-tftpboot- boot image via network using TFTP protocol
-usb	- USB sub-system
-usbboot - boot from USB device
-version - print monitor version
--> usb start
-(Re)start USB...
-USB:   OHCI pci controller (1131, 1561) found @(0:17:0)
-OHCI regs address 0x80000000
-scanning bus for devices... 2 USB Device(s) found
-       scanning bus for storage devices... 1 Storage Device(s) found
-->
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
deleted file mode 100644
index 1568f455e9..0000000000
--- a/board/freescale/m547xevb/m547xevb.c
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	puts("Board: ");
-	puts("Freescale FireEngine 5475 EVB\n");
-	return 0;
-};
-
-int dram_init(void)
-{
-	siu_t *siu = (siu_t *) (MMAP_SIU);
-	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
-	u32 dramsize, i;
-#ifdef CONFIG_SYS_DRAMSZ1
-	u32 temp;
-#endif
-
-	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
-
-	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
-	for (i = 0x13; i < 0x20; i++) {
-		if (dramsize == (1 << i))
-			break;
-	}
-	i--;
-	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
-
-#ifdef CONFIG_SYS_DRAMSZ1
-	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
-	for (i = 0x13; i < 0x20; i++) {
-		if (temp == (1 << i))
-			break;
-	}
-	i--;
-	dramsize += temp;
-	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
-#endif
-
-	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
-	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
-
-	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
-
-	/* Issue LEMR */
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
-
-	udelay(500);
-
-	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
-
-	/* Perform two refresh cycles */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
-
-	out_be32(&sdram->ctrl,
-		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
-
-	udelay(100);
-
-	gd->ram_size = dramsize;
-
-	return 0;
-};
-
-int testdram(void)
-{
-	/* TODO: XXX XXX XXX */
-	printf("DRAM test not implemented!\n");
-
-	return (0);
-}
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI devices, report devices found.
- */
-static struct pci_controller hose;
-extern void pci_mcf547x_8x_init(struct pci_controller *hose);
-
-void pci_init_board(void)
-{
-	pci_mcf547x_8x_init(&hose);
-}
-#endif				/* CONFIG_PCI */
diff --git a/board/freescale/m548xevb/Kconfig b/board/freescale/m548xevb/Kconfig
deleted file mode 100644
index da924e3ce9..0000000000
--- a/board/freescale/m548xevb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M5485EVB
-
-config SYS_CPU
-	default "mcf547x_8x"
-
-config SYS_BOARD
-	default "m548xevb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "M5485EVB"
-
-endif
diff --git a/board/freescale/m548xevb/MAINTAINERS b/board/freescale/m548xevb/MAINTAINERS
deleted file mode 100644
index 4e642e69d5..0000000000
--- a/board/freescale/m548xevb/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-M548XEVB BOARD
-M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
-S:	Maintained
-F:	board/freescale/m548xevb/
-F:	include/configs/M5485EVB.h
-F:	configs/M5485AFE_defconfig
-F:	configs/M5485BFE_defconfig
-F:	configs/M5485CFE_defconfig
-F:	configs/M5485DFE_defconfig
-F:	configs/M5485EFE_defconfig
-F:	configs/M5485FFE_defconfig
-F:	configs/M5485GFE_defconfig
-F:	configs/M5485HFE_defconfig
diff --git a/board/freescale/m548xevb/Makefile b/board/freescale/m548xevb/Makefile
deleted file mode 100644
index 05bfaa3371..0000000000
--- a/board/freescale/m548xevb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	= m548xevb.o
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
deleted file mode 100644
index b62355a7ae..0000000000
--- a/board/freescale/m548xevb/m548xevb.c
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	puts("Board: ");
-	puts("Freescale FireEngine 5485 EVB\n");
-	return 0;
-};
-
-int dram_init(void)
-{
-	siu_t *siu = (siu_t *) (MMAP_SIU);
-	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
-	u32 dramsize, i;
-#ifdef CONFIG_SYS_DRAMSZ1
-	u32 temp;
-#endif
-
-	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
-
-	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
-	for (i = 0x13; i < 0x20; i++) {
-		if (dramsize == (1 << i))
-			break;
-	}
-	i--;
-	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
-
-#ifdef CONFIG_SYS_DRAMSZ1
-	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
-	for (i = 0x13; i < 0x20; i++) {
-		if (temp == (1 << i))
-			break;
-	}
-	i--;
-	dramsize += temp;
-	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
-#endif
-
-	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
-	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
-
-	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
-
-	/* Issue LEMR */
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
-
-	udelay(500);
-
-	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
-
-	/* Perform two refresh cycles */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
-
-	out_be32(&sdram->ctrl,
-		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
-
-	udelay(100);
-
-	gd->ram_size = dramsize;
-
-	return 0;
-};
-
-int testdram(void)
-{
-	/* TODO: XXX XXX XXX */
-	printf("DRAM test not implemented!\n");
-
-	return (0);
-}
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI devices, report devices found.
- */
-static struct pci_controller hose;
-extern void pci_mcf547x_8x_init(struct pci_controller *hose);
-
-void pci_init_board(void)
-{
-	pci_mcf547x_8x_init(&hose);
-}
-#endif				/* CONFIG_PCI */
diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig
deleted file mode 100644
index b6332a1368..0000000000
--- a/board/freescale/mpc8313erdb/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_MPC8313ERDB_NOR
-
-config SYS_BOARD
-	default "mpc8313erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8313ERDB_NOR"
-
-endif
-
-if TARGET_MPC8313ERDB_NAND
-
-config SYS_BOARD
-	default "mpc8313erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8313ERDB_NAND"
-
-endif
diff --git a/board/freescale/mpc8313erdb/MAINTAINERS b/board/freescale/mpc8313erdb/MAINTAINERS
deleted file mode 100644
index 807fb0b6e9..0000000000
--- a/board/freescale/mpc8313erdb/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MPC8313ERDB BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/mpc8313erdb/
-F:	include/configs/MPC8313ERDB.h
-F:	configs/MPC8313ERDB_33_defconfig
-F:	configs/MPC8313ERDB_66_defconfig
-F:	configs/MPC8313ERDB_NAND_33_defconfig
-F:	configs/MPC8313ERDB_NAND_66_defconfig
diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile
deleted file mode 100644
index af600ccdbb..0000000000
--- a/board/freescale/mpc8313erdb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= mpc8313erdb.o sdram.o
diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README
deleted file mode 100644
index 697cee4c42..0000000000
--- a/board/freescale/mpc8313erdb/README
+++ /dev/null
@@ -1,111 +0,0 @@
-Freescale MPC8313ERDB Board
------------------------------------------
-
-1.	Board Switches and Jumpers
-
-	S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
-	To boot the image at 0xFE000000 in NOR flash, use these DIP
-	switch settings for S3 S4:
-
-	+------+	+------+
-	|      |	| **** |
-	| **** |	|      |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	To boot the image at the beginning of NAND flash, use these
-	DIP switch settings for S3 S4:
-
-	+------+	+------+
-	| *    |	|  *** |
-	|  *** |	| *    |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x07ff_ffff	DDR		 128M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xe200_0000	0xe20f_ffff	PCI IO		 16M
-	0xe280_0000	0xe280_7fff	NAND FLASH (CS1) 32K
-	0xf000_0000	0xf001_ffff	VSC7385 (CS2)	 128K
-	0xfa00_0000	0xfa00_7fff	Board Status/	 32K
-					LED Control (CS3)
-	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
-
-	When booting from NAND, NAND flash is CS0 and NOR flash
-	is CS1.
-
-3.	Definitions
-
-3.1	Explanation of NEW definitions in:
-
-	include/configs/MPC8313ERDB.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC831x		MPC831x specific
-	CONFIG_MPC8313ERDB	MPC8313ERDB board specific
-
-4.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8313ERDB_XXX_config
-	(where XXX is:
-	   33 - 33 MHz oscillator, boot from NOR flash
-	   66 - 66 MHz oscillator, boot from NOR flash
-	   NAND_33 - 33 MHz oscillator, boot from NAND flash
-	   NAND_66 - 66 MHz oscillator, boot from NAND flash)
-	make
-
-5.	Downloading and Flashing Images
-
-5.1	Reflash U-Boot Image using U-Boot
-
-	NOR flash:
-
-	=>run tftpflash
-
-	You may want to try
-	=>tftpboot $loadaddr $uboot
-	first, to make sure that the TFTP load will succeed before it
-	goes ahead and wipes out your current firmware.  And of course,
-	have an alternate means of programming the flash available
-	if the new U-Boot doesn't boot.
-
-	NAND flash:
-
-	=>tftpboot $loadaddr <filename>
-	=>nand erase 0 0x80000
-	=>nand write $loadaddr 0 0x80000
-
-	...where 0x80000 is the filesize rounded up to
-	the next 0x20000 increment.
-
-5.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	=>run nfsboot
-	or
-	=>run ramboot
-
-6	Notes
-
-	The console baudrate for MPC8313ERDB is 115200bps.
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
deleted file mode 100644
index 3bf5cff1e1..0000000000
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Author: Scott Wood <scottwood@freescale.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <fdt_support.h>
-#include <init.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#include <pci.h>
-#include <mpc83xx.h>
-#include <vsc7385.h>
-#include <ns16550.h>
-#include <nand.h>
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-#include <asm/gpio.h>
-#endif
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
-#endif
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-	mpc83xx_gpio_init_f();
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-	mpc83xx_gpio_init_r();
-#endif
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8313ERDB\n");
-	return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-static struct pci_region pci_regions[] = {
-	{
-		.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
-		.size = CONFIG_SYS_PCI1_MEM_SIZE,
-		.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
-		.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
-		.size = CONFIG_SYS_PCI1_MMIO_SIZE,
-		.flags = PCI_REGION_MEM
-	},
-	{
-		.bus_start = CONFIG_SYS_PCI1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
-		.size = CONFIG_SYS_PCI1_IO_SIZE,
-		.flags = PCI_REGION_IO
-	}
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci_regions };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-}
-
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
-	int rc = 0;
-
-#ifdef CONFIG_VSC7385_IMAGE
-	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
-		CONFIG_VSC7385_IMAGE_SIZE)) {
-		puts("Failure uploading VSC7385 microcode.\n");
-		rc = 1;
-	}
-#endif
-
-	return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
-#else /* CONFIG_SPL_BUILD */
-void board_init_f(ulong bootflag)
-{
-	board_early_init_f();
-	ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-	puts("NAND boot... ");
-	timer_init();
-	dram_init();
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
-		      CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (gd->flags & GD_FLG_SILENT)
-		return;
-
-	if (c == '\n')
-		ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
-	ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-#endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
deleted file mode 100644
index f146ae5d43..0000000000
--- a/board/freescale/mpc8313erdb/sdram.c
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Authors: Nick.Spence@freescale.com
- *          Wilson.Lo@freescale.com
- *          scottwood@freescale.com
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-static void resume_from_sleep(void)
-{
-	u32 magic = *(u32 *)0;
-
-	typedef void (*func_t)(void);
-	func_t resume = *(func_t *)4;
-
-	if (magic == 0xf5153ae5)
-		resume();
-
-	gd->flags &= ~GD_FLG_SILENT;
-	puts("\nResume from sleep failed: bad magic word\n");
-}
-#endif
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	__udelay(50000);
-
-#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[0].csbnds =
-		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
-			CSBNDS_EA);
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Currently we use only one CS, so disable the other bank. */
-	im->ddr.cs_config[1] = 0;
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
-	else
-#endif
-		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
-
-	im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	sync();
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-#endif
-
-	return msize;
-}
-
-int dram_init(void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &im->im_lbc;
-	u32 msize;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -ENXIO;
-
-	/* DDR SDRAM - Main SODIMM */
-	msize = fixed_sdram();
-
-	/* Local Bus setup lbcr and mrtpr */
-	lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
-	/* LB refresh timer prescal, 266MHz/32 */
-	lbc->mrtpr = 0x20000000;
-	sync();
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		resume_from_sleep();
-#endif
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	gd->ram_size = msize;
-
-	return 0;
-}
diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig
deleted file mode 100644
index f76b0d1d6d..0000000000
--- a/board/freescale/mpc8315erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8315ERDB
-
-config SYS_BOARD
-	default "mpc8315erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8315ERDB"
-
-endif
diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS
deleted file mode 100644
index cdac1ac2ee..0000000000
--- a/board/freescale/mpc8315erdb/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8315ERDB BOARD
-#M:	Dave Liu <daveliu@freescale.com>
-S:	Orphan (since 2018-05)
-F:	board/freescale/mpc8315erdb/
-F:	include/configs/MPC8315ERDB.h
-F:	configs/MPC8315ERDB_defconfig
-F:	configs/MPC8315ERDB_NANDSPL_defconfig
diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile
deleted file mode 100644
index 579181999d..0000000000
--- a/board/freescale/mpc8315erdb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= mpc8315erdb.o sdram.o
diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README
deleted file mode 100644
index 8ad6d810c7..0000000000
--- a/board/freescale/mpc8315erdb/README
+++ /dev/null
@@ -1,105 +0,0 @@
-Freescale MPC8315ERDB Board
------------------------------------------
-
-1.	Board Switches and Jumpers
-
-	S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
-	To boot the image at 0xFE000000 in NOR flash, use these DIP
-	switch settings for S3 S4:
-
-	+------+	+------+
-	|      |	| **** |
-	| **** |	|      |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	To boot the image at the beginning of NAND flash, use these
-	DIP switch settings for S3 S4:
-
-	+------+	+------+
-	| *    |	|  *** |
-	|  *** |	| *    |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x07ff_ffff	DDR		 128M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xe030_0000	0xe03f_ffff	PCI IO		 1M
-	0xe060_0000	0xe060_7fff	NAND FLASH (CS1) 32K
-	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
-
-	When booting from NAND, NAND flash is CS0 and NOR flash
-	is CS1.
-
-3.	Definitions
-
-3.1	Explanation of NEW definitions in:
-
-	include/configs/MPC8315ERDB.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC831x		MPC831x specific
-	CONFIG_MPC8315		MPC8315 specific
-	CONFIG_MPC8315ERDB	MPC8315ERDB board specific
-
-4.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
-	make all
-
-5.	Downloading and Flashing Images
-
-5.1	Reflash U-Boot Image using U-Boot
-
-	NOR flash:
-
-	tftp 40000 u-boot.bin
-	protect off all
-	erase fe000000 fe1fffff
-
-	cp.b 40000 fe000000 xxxx
-	protect on all
-
-	You have to supply the correct byte count with 'xxxx'
-	from the TFTP result log.
-
-	NAND flash:
-
-	=>tftpboot $loadaddr <filename>
-	=>nand erase 0 0x80000
-	=>nand write $loadaddr 0 0x80000
-
-	...where 0x80000 is the filesize rounded up to
-	the next 0x20000 increment.
-
-5.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	=>run nfsboot
-	or
-	=>run ramboot
-
-6	Notes
-
-	The console baudrate for MPC8315ERDB is 115200bps.
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
deleted file mode 100644
index e89d5d4955..0000000000
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ /dev/null
@@ -1,249 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Author: Scott Wood <scottwood@freescale.com>
- *         Dave Liu <daveliu@freescale.com>
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
-
-	return 0;
-}
-
-#ifndef CONFIG_NAND_SPL
-
-static u8 read_board_info(void)
-{
-	u8 val8;
-	i2c_set_bus_num(0);
-
-	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
-		return val8;
-	else
-		return 0;
-}
-
-int checkboard(void)
-{
-	static const char * const rev_str[] = {
-		"0.0",
-		"0.1",
-		"1.0",
-		"1.1",
-		"<unknown>",
-	};
-	u8 info;
-	int i;
-
-	info = read_board_info();
-	i = (!info) ? 4: info & 0x03;
-
-	printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
-
-	return 0;
-}
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
-		size: CONFIG_SYS_PCI_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
-		size: CONFIG_SYS_PCI_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_IO_BASE,
-		phys_start: CONFIG_SYS_PCI_IO_PHYS,
-		size: CONFIG_SYS_PCI_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static struct pci_region pcie_regions_1[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-		.size = CONFIG_SYS_PCIE2_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile sysconf83xx_t *sysconf = &immr->sysconf;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *reg[] = { pci_regions };
-	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Configure the clock for PCIE controller */
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
-				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	out_be32(&sysconf->pecr2, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(2, pcie_reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_tsec1_fixup(void *fdt, struct bd_info *bd)
-{
-	const char disabled[] = "disabled";
-	const char *path;
-	int ret;
-
-	if (hwconfig_arg_cmp("board_type", "tsec1")) {
-		return;
-	} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
-		printf("NOTICE: No or unknown board_type hwconfig specified.\n"
-		       "        Assuming board with TSEC1.\n");
-		return;
-	}
-
-	ret = fdt_path_offset(fdt, "/aliases");
-	if (ret < 0) {
-		printf("WARNING: can't find /aliases node\n");
-		return;
-	}
-
-	path = fdt_getprop(fdt, ret, "ethernet0", NULL);
-	if (!path) {
-		printf("WARNING: can't find ethernet0 alias\n");
-		return;
-	}
-
-	do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	fsl_fdt_fixup_dr_usb(blob, bd);
-	fdt_tsec1_fixup(blob, bd);
-
-	return 0;
-}
-#endif
-
-int board_eth_init(struct bd_info *bis)
-{
-	cpu_eth_init(bis);	/* Initialize TSECs first */
-	return pci_eth_init(bis);
-}
-
-#else /* CONFIG_NAND_SPL */
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8315ERDB\n");
-	return 0;
-}
-
-void board_init_f(ulong bootflag)
-{
-	board_early_init_f();
-	ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-	puts("NAND boot... ");
-	timer_init();
-	dram_init();
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
-		      CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (gd->flags & GD_FLG_SILENT)
-		return;
-
-	if (c == '\n')
-		ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
-	ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-
-#endif /* CONFIG_NAND_SPL */
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
deleted file mode 100644
index ffbb79aaec..0000000000
--- a/board/freescale/mpc8315erdb/sdram.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Authors: Nick.Spence@freescale.com
- *          Wilson.Lo@freescale.com
- *          scottwood@freescale.com
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void resume_from_sleep(void)
-{
-	u32 magic = *(u32 *)0;
-
-	typedef void (*func_t)(void);
-	func_t resume = *(func_t *)4;
-
-	if (magic == 0xf5153ae5)
-		resume();
-
-	gd->flags &= ~GD_FLG_SILENT;
-	puts("\nResume from sleep failed: bad magic word\n");
-}
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-#ifndef CONFIG_SYS_RAMBOOT
-static long fixed_sdram(void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE  & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	__udelay(50000);
-
-	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Currently we use only one CS, so disable the other bank. */
-	im->ddr.cs_config[1] = 0;
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
-	else
-		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	sync();
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	sync();
-
-	return msize;
-}
-#else
-static long fixed_sdram(void)
-{
-	return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-int dram_init(void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -ENXIO;
-
-	/* DDR SDRAM */
-	msize = fixed_sdram();
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		resume_from_sleep();
-
-	/* set total bus SDRAM size(bytes)  -- DDR */
-	gd->ram_size = msize;
-
-	return 0;
-}
diff --git a/board/freescale/mpc8323erdb/Kconfig b/board/freescale/mpc8323erdb/Kconfig
deleted file mode 100644
index acf8122196..0000000000
--- a/board/freescale/mpc8323erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8323ERDB
-
-config SYS_BOARD
-	default "mpc8323erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8323ERDB"
-
-endif
diff --git a/board/freescale/mpc8323erdb/MAINTAINERS b/board/freescale/mpc8323erdb/MAINTAINERS
deleted file mode 100644
index 496ab2af27..0000000000
--- a/board/freescale/mpc8323erdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8323ERDB BOARD
-#M:	Michael Barkowski <michael.barkowski@freescale.com>
-S:	Orphan (since 2018-05)
-F:	board/freescale/mpc8323erdb/
-F:	include/configs/MPC8323ERDB.h
-F:	configs/MPC8323ERDB_defconfig
diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile
deleted file mode 100644
index e6f61891d9..0000000000
--- a/board/freescale/mpc8323erdb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= mpc8323erdb.o
diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README
deleted file mode 100644
index 9a46da0781..0000000000
--- a/board/freescale/mpc8323erdb/README
+++ /dev/null
@@ -1,71 +0,0 @@
-Freescale MPC8323ERDB Board
------------------------------------------
-
-1.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x03ff_ffff	DDR		 64M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xd000_0000	0xd3ff_ffff	PCI IO		 64M
-	0xfe00_0000	0xfeff_ffff	NOR FLASH (CS0)	 16M
-
-2.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8323ERDB_config
-	make
-
-3.	Downloading and Flashing Images
-
-3.1	Reflash U-Boot Image using U-Boot
-
-	N.b, have an alternate means of programming
-	the flash available if the new U-Boot doesn't boot.
-
-	First try a:
-
-	tftpboot $loadaddr $uboot
-
-	to make sure that the TFTP load will succeed before
-	an erase goes ahead and wipes out your current firmware.
-	Then do a:
-
-	run tftpflash
-
-	which is a shorter version of the manual sequence:
-
-	tftp $loadaddr u-boot.bin
-	protect off fe000000 +$filesize
-	erase fe000000 +$filesize
-	cp.b $loadaddr fe000000 $filesize
-
-	To keep your old U-Boot's environment variables, do a:
-
-	saveenv
-
-	prior to resetting the board.
-
-3.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	run nfsboot
-
-	or
-
-	run ramboot
-
-4	Notes
-
-	The console baudrate for MPC8323ERDB is 115200bps.
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
deleted file mode 100644
index cef3216a6f..0000000000
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Michael Barkowski <michael.barkowski@freescale.com>
- * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <eeprom.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <u-boot/crc.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* UCC3 */
-	{1,  0, 1, 0, 1}, /* TxD0 */
-	{1,  1, 1, 0, 1}, /* TxD1 */
-	{1,  2, 1, 0, 1}, /* TxD2 */
-	{1,  3, 1, 0, 1}, /* TxD3 */
-	{1,  9, 1, 0, 1}, /* TxER */
-	{1, 12, 1, 0, 1}, /* TxEN */
-	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
-	{1,  4, 2, 0, 1}, /* RxD0 */
-	{1,  5, 2, 0, 1}, /* RxD1 */
-	{1,  6, 2, 0, 1}, /* RxD2 */
-	{1,  7, 2, 0, 1}, /* RxD3 */
-	{1,  8, 2, 0, 1}, /* RxER */
-	{1, 10, 2, 0, 1}, /* RxDV */
-	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
-	{1, 11, 2, 0, 1}, /* COL */
-	{1, 13, 2, 0, 1}, /* CRS */
-
-	/* UCC2 */
-	{0, 18, 1, 0, 1}, /* TxD0 */
-	{0, 19, 1, 0, 1}, /* TxD1 */
-	{0, 20, 1, 0, 1}, /* TxD2 */
-	{0, 21, 1, 0, 1}, /* TxD3 */
-	{0, 27, 1, 0, 1}, /* TxER */
-	{0, 30, 1, 0, 1}, /* TxEN */
-	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
-
-	{0, 22, 2, 0, 1}, /* RxD0 */
-	{0, 23, 2, 0, 1}, /* RxD1 */
-	{0, 24, 2, 0, 1}, /* RxD2 */
-	{0, 25, 2, 0, 1}, /* RxD3 */
-	{0, 26, 1, 0, 1}, /* RxER */
-	{0, 28, 2, 0, 1}, /* Rx_DV */
-	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
-	{0, 29, 2, 0, 1}, /* COL */
-	{0, 31, 2, 0, 1}, /* CRS */
-
-	{3,  4, 3, 0, 2}, /* MDIO */
-	{3,  5, 1, 0, 2}, /* MDC */
-
-	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int fixed_sdram(void);
-
-int dram_init(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -ENXIO;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-
-	msize = fixed_sdram();
-
-	/* set total bus SDRAM size(bytes)  -- DDR */
-	gd->ram_size = msize * 1024 * 1024;
-
-	return 0;
-}
-
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-	}
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	__asm__ __volatile__ ("sync");
-	udelay(200);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	__asm__ __volatile__ ("sync");
-	return msize;
-}
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8323ERDB\n");
-	return 0;
-}
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci_regions };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
-int mac_read_from_eeprom(void)
-{
-	uchar buf[28];
-	char str[18];
-	int i = 0;
-	unsigned int crc = 0;
-	unsigned char enetvar[32];
-
-	/* Read MAC addresses from EEPROM */
-	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
-		printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
-		       CONFIG_SYS_I2C_EEPROM_ADDR);
-	} else {
-		uint32_t crc_buf;
-
-		memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
-
-		if (crc32(crc, buf, 24) == crc_buf) {
-			printf("Reading MAC from EEPROM\n");
-			for (i = 0; i < 4; i++) {
-				if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
-					sprintf(str,
-						"%02X:%02X:%02X:%02X:%02X:%02X",
-						buf[i * 6], buf[i * 6 + 1],
-						buf[i * 6 + 2], buf[i * 6 + 3],
-						buf[i * 6 + 4], buf[i * 6 + 5]);
-					sprintf((char *)enetvar,
-						i ? "eth%daddr" : "ethaddr", i);
-					env_set((char *)enetvar, str);
-				}
-			}
-		}
-	}
-	return 0;
-}
-#endif				/* CONFIG_I2C_MAC_OFFSET */
diff --git a/board/freescale/mpc832xemds/Kconfig b/board/freescale/mpc832xemds/Kconfig
deleted file mode 100644
index e4cfa15a6f..0000000000
--- a/board/freescale/mpc832xemds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC832XEMDS
-
-config SYS_BOARD
-	default "mpc832xemds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC832XEMDS"
-
-endif
diff --git a/board/freescale/mpc832xemds/MAINTAINERS b/board/freescale/mpc832xemds/MAINTAINERS
deleted file mode 100644
index 232658a203..0000000000
--- a/board/freescale/mpc832xemds/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-MPC832XEMDS BOARD
-#M:	Dave Liu <daveliu@freescale.com>
-S:	Orphan (since 2018-05)
-F:	board/freescale/mpc832xemds/
-F:	include/configs/MPC832XEMDS.h
-F:	configs/MPC832XEMDS_defconfig
-F:	configs/MPC832XEMDS_ATM_defconfig
-F:	configs/MPC832XEMDS_HOST_33_defconfig
-F:	configs/MPC832XEMDS_HOST_66_defconfig
-F:	configs/MPC832XEMDS_SLAVE_defconfig
diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile
deleted file mode 100644
index b1551bf478..0000000000
--- a/board/freescale/mpc832xemds/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc832xemds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README
deleted file mode 100644
index d141cd33e7..0000000000
--- a/board/freescale/mpc832xemds/README
+++ /dev/null
@@ -1,128 +0,0 @@
-Freescale MPC832XEMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
-	For some reason, the HW designers describe the switch settings
-	in terms of 0 and 1, and then map that to physical switches where
-	the label "On" refers to logic 0 and "Off" is logic 1.
-
-	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
-	bits may contribute to signals that are numbered based at 0,
-	and some of those signals may be high-bit-number-0 too.  Heed
-	well the names and labels and do not get confused.
-
-		"Off" == 1
-		"On"  == 0
-
-	SW3 is switch 18 as silk-screened onto the board.
-	SW4[8] is the bit labeled 8 on Switch 4.
-	SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
-	SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
-	SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
-		and bits labeled 8 is set as "Off".
-
-1.1 For the MPC832XEMDS PROTO Board
-
-	First, make sure the board default setting is consistent with the document
-		 shipped with your board. Then apply the following setting:
-	SW3[1-8]= 0000_1000  (core PLL setting, core enable)
-	SW4[1-8]= 0001_0010  (Flash boot on local bus, system PLL setting)
-	SW5[1-8]= 0010_0110  (Boot from high end)
-	SW6[1-8]= 0011_0100  (Flash boot on 16 bit local bus)
-	SW7[1-8]= 1000_0011  (QE PLL setting)
-
-	ENET3/4 MII mode settings:
-	J1 1-2 (ETH3_TXER)
-	J2 2-3 (MII mode)
-	J3 2-3 (MII mode)
-	J4 2-3 (ADSL clockOscillator)
-	J5 1-2 (ETH4_TXER)
-	J6 2-3 (ClockOscillator)
-	JP1 removed (don't force PORESET)
-	JP2 mounted (ETH4/2 MII)
-	JP3 mounted (ETH3 MII)
-	JP4 mounted (HRCW from BCSR)
-
-	ENET3/4 RMII mode settings:
-	J1 1-2 (ETH3_TXER)
-	J2 1-2 (RMII mode)
-	J3 1-2 (RMII mode)
-	J4 2-3 (ADSL clockOscillator)
-	J5 1-2 (ETH4_TXER)
-	J6 2-3 (ClockOscillator)
-	JP1 removed (don't force PORESET)
-	JP2 removed (ETH4/2 RMII)
-	JP3 removed (ETH3 RMII)
-	JP4 removed (HRCW from FLASH)
-
-	on board Oscillator: 66M
-
-
-2. Memory Map
-
-2.1 The memory map should look pretty much like this:
-
-	0x0000_0000	0x7fff_ffff	DDR			2G
-	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
-	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
-	0xc000_0000	0xdfff_ffff	Empty			512M
-	0xe000_0000	0xe01f_ffff	Int Mem Reg Space	2M
-	0xe020_0000	0xe02f_ffff	Empty			1M
-	0xe030_0000	0xe03f_ffff	PCI IO			1M
-	0xe040_0000	0xefff_ffff	Empty			252M
-	0xf400_0000	0xf7ff_ffff	Empty			64M
-	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
-	0xf800_8000	0xf800_ffff	PIB CS2			32K
-	0xf801_0000	0xf801_7fff	PIB CS3			32K
-	0xfe00_0000	0xfeff_ffff	FLASH on CS0		16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
-	include/configs/MPC832XEPB.h
-
-    CONFIG_MPC83xx	MPC83xx family for MPC8349, MPC8360 and MPC832x
-    CONFIG_MPC832x	MPC832x specific
-    CONFIG_MPC832XEMDS	MPC832XEMDS board specific
-
-4. Compilation
-
-	Assuming you're using BASH shell:
-
-		export CROSS_COMPILE=your-cross-compile-prefix
-		cd u-boot
-		make distclean
-		make MPC832XEMDS_config
-		make
-
-	MPC832x support PCI 33MHz and PCI 66MHz, to make U-Boot support PCI:
-
-		1)Make sure the DIP SW support PCI mode as described in Section 1.1.
-
-		2)To Make U-Boot image support PCI 33MHz, use
-			Make MPC832XEMDS_HOST_33_config
-
-		3)To Make U-Boot image support PCI 66MHz, use
-			Make MPC832XEMDS_HOST_66M_config
-
-5. Downloading and Flashing Images
-
-5.0 Download over network:
-
-	tftp 10000 u-boot.bin
-
-5.1 Reflash U-Boot Image using U-Boot
-
-	tftp 20000 u-boot.bin
-	protect off fe000000 fe0fffff
-	erase fe000000 fe0fffff
-	cp.b 20000 fe000000 xxxx
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-Maybe 3ffff will work too, that corresponds to the erased sectors.
-
-
-6. Notes
-	1) The console baudrate for MPC832XEMDS is 115200bps.
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
deleted file mode 100644
index f34758a947..0000000000
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ /dev/null
@@ -1,173 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* ETH3 */
-	{1,  0, 1, 0, 1}, /* TxD0 */
-	{1,  1, 1, 0, 1}, /* TxD1 */
-	{1,  2, 1, 0, 1}, /* TxD2 */
-	{1,  3, 1, 0, 1}, /* TxD3 */
-	{1,  9, 1, 0, 1}, /* TxER */
-	{1, 12, 1, 0, 1}, /* TxEN */
-	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
-	{1,  4, 2, 0, 1}, /* RxD0 */
-	{1,  5, 2, 0, 1}, /* RxD1 */
-	{1,  6, 2, 0, 1}, /* RxD2 */
-	{1,  7, 2, 0, 1}, /* RxD3 */
-	{1,  8, 2, 0, 1}, /* RxER */
-	{1, 10, 2, 0, 1}, /* RxDV */
-	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
-	{1, 11, 2, 0, 1}, /* COL */
-	{1, 13, 2, 0, 1}, /* CRS */
-
-	/* ETH4 */
-	{1, 18, 1, 0, 1}, /* TxD0 */
-	{1, 19, 1, 0, 1}, /* TxD1 */
-	{1, 20, 1, 0, 1}, /* TxD2 */
-	{1, 21, 1, 0, 1}, /* TxD3 */
-	{1, 27, 1, 0, 1}, /* TxER */
-	{1, 30, 1, 0, 1}, /* TxEN */
-	{3,  6, 2, 0, 1}, /* TxCLK->CLK8 */
-
-	{1, 22, 2, 0, 1}, /* RxD0 */
-	{1, 23, 2, 0, 1}, /* RxD1 */
-	{1, 24, 2, 0, 1}, /* RxD2 */
-	{1, 25, 2, 0, 1}, /* RxD3 */
-	{1, 26, 1, 0, 1}, /* RxER */
-	{1, 28, 2, 0, 1}, /* Rx_DV */
-	{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
-	{1, 29, 2, 0, 1}, /* COL */
-	{1, 31, 2, 0, 1}, /* CRS */
-
-	{3,  4, 3, 0, 2}, /* MDIO */
-	{3,  5, 1, 0, 2}, /* MDC */
-
-	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int board_early_init_f(void)
-{
-	volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
-
-	/* Enable flash write */
-	bcsr[9] &= ~0x08;
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_PQ_MDS_PIB
-	pib_init();
-#endif
-	return 0;
-}
-
-int fixed_sdram(void);
-
-int dram_init(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -ENXIO;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-
-	msize = fixed_sdram();
-
-	/* set total bus SDRAM size(bytes)  -- DDR */
-	gd->ram_size = msize * 1024 * 1024;
-
-	return 0;
-}
-
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-	}
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CONFIG_SYS_DDR_SIZE != 128)
-#warning Currenly any ddr size other than 128 is not supported
-#endif
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	__asm__ __volatile__ ("sync");
-	udelay(200);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	__asm__ __volatile__ ("sync");
-	return msize;
-}
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC832XEMDS\n");
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
deleted file mode 100644
index 944108f631..0000000000
--- a/board/freescale/mpc832xemds/pci.c
+++ /dev/null
@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-/*
- * PCI Configuration space access support for MPC83xx PCI Bridge
- */
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-#include "../common/pq-mds-pib.h"
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
-		size: CONFIG_SYS_PCI2_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_IO_BASE,
-		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
-		size: CONFIG_SYS_PCI2_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
-		size: CONFIG_SYS_PCI2_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-#endif
-
-void pci_init_board(void)
-#ifdef CONFIG_PCISLAVE
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
-	struct pci_region *reg[] = { pci1_regions };
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	mpc83xx_pci_init(1, reg);
-
-	/*
-	 * Configure PCI Inbound Translation Windows
-	 */
-	pci_ctrl[0].pitar0 = 0x0;
-	pci_ctrl[0].pibar0 = 0x0;
-	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
-	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-
-	pci_ctrl[0].pitar1 = 0x0;
-	pci_ctrl[0].pibar1 = 0x0;
-	pci_ctrl[0].piebar1 = 0x0;
-	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-
-	pci_ctrl[0].pitar2 = 0x0;
-	pci_ctrl[0].pibar2 = 0x0;
-	pci_ctrl[0].piebar2 = 0x0;
-	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-
-	/* Unlock the configuration bit */
-	mpc83xx_pcislave_unlock(0);
-	printf("PCI:   Agent mode enabled\n");
-}
-#else
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
-	/* initialize the PCA9555PW IO expander on the PIB board */
-	pib_init();
-
-#if defined(CONFIG_PCI_66M)
-	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
-	printf("PCI clock is 66MHz\n");
-#elif defined(CONFIG_PCI_33M)
-	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
-	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
-	printf("PCI clock is 33MHz\n");
-#else
-	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
-	printf("PCI clock is 66MHz\n");
-#endif
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
-#endif				/* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8541cds/Kconfig b/board/freescale/mpc8541cds/Kconfig
deleted file mode 100644
index 034eab2544..0000000000
--- a/board/freescale/mpc8541cds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8541CDS
-
-config SYS_BOARD
-	default "mpc8541cds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8541CDS"
-
-endif
diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS
deleted file mode 100644
index cf3b9cf5f7..0000000000
--- a/board/freescale/mpc8541cds/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8541CDS BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8541cds/
-F:	include/configs/MPC8541CDS.h
-F:	configs/MPC8541CDS_defconfig
-F:	configs/MPC8541CDS_legacy_defconfig
diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile
deleted file mode 100644
index b2b721ac92..0000000000
--- a/board/freescale/mpc8541cds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= mpc8541cds.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
deleted file mode 100644
index 05c56a85d2..0000000000
--- a/board/freescale/mpc8541cds/ddr.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 6;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 0;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c
deleted file mode 100644
index 69f151b615..0000000000
--- a/board/freescale/mpc8541cds/law.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
- * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
- * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
- * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
-	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
deleted file mode 100644
index 5b4fbd5e30..0000000000
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ /dev/null
@@ -1,429 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004, 2011 Freescale Semiconductor.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <vsprintf.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <spd_sdram.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-#include "../common/cadmus.h"
-#include "../common/eeprom.h"
-#include "../common/via.h"
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-void local_bus_init(void);
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
-	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
-	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
-	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
-	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
-	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
-	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
-	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
-	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
-	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
-	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
-	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
-	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
-	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
-	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
-	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
-	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
-	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
-	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
-	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
-	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
-	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
-	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
-	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
-	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
-	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
-	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
-	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
-	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
-	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
-	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
-	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
-	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
-	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
-    },
-
-    /* Port D */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
-	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
-	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-int checkboard (void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	char buf[32];
-
-	/* PCI slot in USER bits CSR[6:7] by convention. */
-	uint pci_slot = get_pci_slot ();
-
-	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
-	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
-	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
-	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
-
-	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
-
-	uint cpu_board_rev = get_cpu_board_revision ();
-
-	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
-		get_board_version (), pci_slot);
-
-	printf ("CPU Board Revision %d.%d (0x%04x)\n",
-		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
-		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
-	printf("PCI1: %d bit, %s MHz, %s\n",
-		(pci1_32) ? 32 : 64,
-		strmhz(buf, pci1_speed),
-		pci1_clk_sel ? "sync" : "async");
-
-	if (pci_dual) {
-		printf("PCI2: 32 bit, 66 MHz, %s\n",
-			pci2_clk_sel ? "sync" : "async");
-	} else {
-		printf("PCI2: disabled\n");
-	}
-
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init ();
-
-	return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	uint clkdiv;
-	uint lbc_hz;
-	sys_info_t sysinfo;
-	uint temp_lbcdll;
-
-	/*
-	 * Errata LBC11.
-	 * Fix Local Bus clock glitch when DLL is enabled.
-	 *
-	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
-	 * If localbus freq is > 133MHz, DLL can be safely enabled.
-	 * Between 66 and 133, the DLL is enabled with an override workaround.
-	 */
-
-	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & LCRR_CLKDIV;
-	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
-
-	if (lbc_hz < 66) {
-		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */
-
-	} else if (lbc_hz >= 133) {
-		lbc->lcrr &= (~LCRR_DBYP);		/* DLL Enabled */
-
-	} else {
-		lbc->lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
-		udelay(200);
-
-		/*
-		 * Sample LBC DLL ctrl reg, upshift it to set the
-		 * override bits.
-		 */
-		temp_lbcdll = gur->lbcdllcr;
-		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
-		asm("sync;isync;msync");
-	}
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-
-	uint idx;
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-	uint cpu_board_rev;
-	uint lsdmr_common;
-
-	puts("LBC SDRAM: ");
-	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
-		   "\n       ");
-
-	/*
-	 * Setup SDRAM Base and Option Registers
-	 */
-	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	asm("msync");
-
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	asm("msync");
-
-	/*
-	 * Determine which address lines to use baed on CPU board rev.
-	 */
-	cpu_board_rev = get_cpu_board_revision();
-	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
-	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
-		lsdmr_common |= LSDMR_BSMA1617;
-	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
-		lsdmr_common |= LSDMR_BSMA1516;
-	} else {
-		/*
-		 * Assume something unable to identify itself is
-		 * really old, and likely has lines 16/17 mapped.
-		 */
-		lsdmr_common |= LSDMR_BSMA1617;
-	}
-
-	/*
-	 * Issue PRECHARGE ALL command.
-	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	/*
-	 * Issue 8 AUTO REFRESH commands.
-	 */
-	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
-		asm("sync;msync");
-		*sdram_addr = 0xff;
-		ppcDcbf((unsigned long) sdram_addr);
-		udelay(100);
-	}
-
-	/*
-	 * Issue 8 MODE-set command.
-	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	/*
-	 * Issue NORMAL OP command.
-	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
-
-#endif	/* enable SDRAM init */
-}
-
-#if defined(CONFIG_PCI)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device.  Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
-	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
-	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
-		mpc85xx_config_via_usbide, {0,0,0}},
-	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
-		mpc85xx_config_via_usb, {0,0,0}},
-	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
-		mpc85xx_config_via_usb2, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
-		mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
-		mpc85xx_config_via_ac97, {0,0,0}},
-	{},
-};
-
-static struct pci_controller hose[] = {
-	{ config_table: pci_mpc85xxcds_config_table,},
-#ifdef CONFIG_MPC85XX_PCI2
-	{},
-#endif
-};
-
-#endif	/* CONFIG_PCI */
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
-	pci_mpc85xx_init(hose);
-#endif
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_pci_setup(void *blob, struct bd_info *bd)
-{
-	int node, tmp[2];
-	const char *path;
-
-	node = fdt_path_offset(blob, "/aliases");
-	tmp[0] = 0;
-	if (node >= 0) {
-#ifdef CONFIG_PCI1
-		path = fdt_getprop(blob, node, "pci0", NULL);
-		if (path) {
-			tmp[1] = hose[0].last_busno - hose[0].first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
-#endif
-#ifdef CONFIG_MPC85XX_PCI2
-		path = fdt_getprop(blob, node, "pci1", NULL);
-		if (path) {
-			tmp[1] = hose[1].last_busno - hose[1].first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
-#endif
-	}
-}
-#endif
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
deleted file mode 100644
index d4ed51c543..0000000000
--- a/board/freescale/mpc8541cds/tlb.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_16M, 1),
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xa0000000	256M	PCI2 MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xb0000000	256M	PCI2 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 * 0xe300_0000	16M	PCI2 IO
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 6, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 7:	1M	Non-cacheable, guarded
-	 * 0xf8000000	1M	CADMUS registers
-	 */
-	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_1M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8555cds/Kconfig b/board/freescale/mpc8555cds/Kconfig
deleted file mode 100644
index 04bd572212..0000000000
--- a/board/freescale/mpc8555cds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8555CDS
-
-config SYS_BOARD
-	default "mpc8555cds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8555CDS"
-
-endif
diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS
deleted file mode 100644
index 8f32febd91..0000000000
--- a/board/freescale/mpc8555cds/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8555CDS BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8555cds/
-F:	include/configs/MPC8555CDS.h
-F:	configs/MPC8555CDS_defconfig
-F:	configs/MPC8555CDS_legacy_defconfig
diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile
deleted file mode 100644
index f121c2fa6b..0000000000
--- a/board/freescale/mpc8555cds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= mpc8555cds.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
deleted file mode 100644
index 05c56a85d2..0000000000
--- a/board/freescale/mpc8555cds/ddr.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 6;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 0;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c
deleted file mode 100644
index 69f151b615..0000000000
--- a/board/freescale/mpc8555cds/law.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
- * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
- * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
- * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
-	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
deleted file mode 100644
index 3bb8e769c8..0000000000
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ /dev/null
@@ -1,430 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004, 2011 Freescale Semiconductor.
- */
-
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <vsprintf.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <spd_sdram.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-#include "../common/cadmus.h"
-#include "../common/eeprom.h"
-#include "../common/via.h"
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-void local_bus_init(void);
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
-	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
-	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
-	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
-	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
-	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
-	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
-	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
-	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
-	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
-	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
-	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
-	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
-	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
-	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
-	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
-	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
-	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
-	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
-	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
-	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
-	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
-	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
-	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
-	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
-	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
-	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
-	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
-	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
-	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
-	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
-	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
-	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
-	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
-    },
-
-    /* Port D */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
-	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
-	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-int checkboard (void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	char buf[32];
-
-	/* PCI slot in USER bits CSR[6:7] by convention. */
-	uint pci_slot = get_pci_slot ();
-
-	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
-	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
-	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
-	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
-
-	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
-
-	uint cpu_board_rev = get_cpu_board_revision ();
-
-	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
-		get_board_version (), pci_slot);
-
-	printf ("CPU Board Revision %d.%d (0x%04x)\n",
-		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
-		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
-	printf("PCI1: %d bit, %s MHz, %s\n",
-		(pci1_32) ? 32 : 64,
-		strmhz(buf, pci1_speed),
-		pci1_clk_sel ? "sync" : "async");
-
-	if (pci_dual) {
-		printf("PCI2: 32 bit, 66 MHz, %s\n",
-			pci2_clk_sel ? "sync" : "async");
-	} else {
-		printf("PCI2: disabled\n");
-	}
-
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init ();
-
-	return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	uint clkdiv;
-	uint lbc_hz;
-	sys_info_t sysinfo;
-	uint temp_lbcdll;
-
-	/*
-	 * Errata LBC11.
-	 * Fix Local Bus clock glitch when DLL is enabled.
-	 *
-	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
-	 * If localbus freq is > 133MHz, DLL can be safely enabled.
-	 * Between 66 and 133, the DLL is enabled with an override workaround.
-	 */
-
-	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & LCRR_CLKDIV;
-	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
-
-	if (lbc_hz < 66) {
-		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */
-
-	} else if (lbc_hz >= 133) {
-		lbc->lcrr &= (~LCRR_DBYP);		/* DLL Enabled */
-
-	} else {
-		lbc->lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
-		udelay(200);
-
-		/*
-		 * Sample LBC DLL ctrl reg, upshift it to set the
-		 * override bits.
-		 */
-		temp_lbcdll = gur->lbcdllcr;
-		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
-		asm("sync;isync;msync");
-	}
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-
-	uint idx;
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-	uint cpu_board_rev;
-	uint lsdmr_common;
-
-	puts("LBC SDRAM: ");
-	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
-		   "\n       ");
-
-	/*
-	 * Setup SDRAM Base and Option Registers
-	 */
-	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	asm("msync");
-
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	asm("msync");
-
-	/*
-	 * Determine which address lines to use baed on CPU board rev.
-	 */
-	cpu_board_rev = get_cpu_board_revision();
-	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
-	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
-		lsdmr_common |= LSDMR_BSMA1617;
-	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
-		lsdmr_common |= LSDMR_BSMA1516;
-	} else {
-		/*
-		 * Assume something unable to identify itself is
-		 * really old, and likely has lines 16/17 mapped.
-		 */
-		lsdmr_common |= LSDMR_BSMA1617;
-	}
-
-	/*
-	 * Issue PRECHARGE ALL command.
-	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	/*
-	 * Issue 8 AUTO REFRESH commands.
-	 */
-	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
-		asm("sync;msync");
-		*sdram_addr = 0xff;
-		ppcDcbf((unsigned long) sdram_addr);
-		udelay(100);
-	}
-
-	/*
-	 * Issue 8 MODE-set command.
-	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	/*
-	 * Issue NORMAL OP command.
-	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
-
-#endif	/* enable SDRAM init */
-}
-
-#ifdef CONFIG_PCI
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device.  Work around that by refusing to configure it
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
-	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
-	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
-		mpc85xx_config_via_usbide, {0,0,0}},
-	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
-		mpc85xx_config_via_usb, {0,0,0}},
-	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
-		mpc85xx_config_via_usb2, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
-		mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
-		mpc85xx_config_via_ac97, {0,0,0}},
-	{},
-};
-
-
-static struct pci_controller hose[] = {
-	{
-	config_table: pci_mpc85xxcds_config_table,
-	},
-#ifdef CONFIG_MPC85XX_PCI2
-	{},
-#endif
-};
-
-#endif
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
-	pci_mpc85xx_init(hose);
-#endif
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_pci_setup(void *blob, struct bd_info *bd)
-{
-	int node, tmp[2];
-	const char *path;
-
-	node = fdt_path_offset(blob, "/aliases");
-	tmp[0] = 0;
-	if (node >= 0) {
-#ifdef CONFIG_PCI1
-		path = fdt_getprop(blob, node, "pci0", NULL);
-		if (path) {
-			tmp[1] = hose[0].last_busno - hose[0].first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
-#endif
-#ifdef CONFIG_MPC85XX_PCI2
-		path = fdt_getprop(blob, node, "pci1", NULL);
-		if (path) {
-			tmp[1] = hose[1].last_busno - hose[1].first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
-#endif
-	}
-}
-#endif
diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c
deleted file mode 100644
index 4a18f05af0..0000000000
--- a/board/freescale/mpc8555cds/tlb.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_16M, 1),
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xa0000000	256M	PCI2 MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xb0000000	256M	PCI2 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 * 0xe300_0000	16M	PCI2 IO
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 6, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 7:	1M	Non-cacheable, guarded
-	 * 0xf8000000	1M	CADMUS registers
-	 */
-	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_1M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8568mds/Kconfig b/board/freescale/mpc8568mds/Kconfig
deleted file mode 100644
index 4e178c5039..0000000000
--- a/board/freescale/mpc8568mds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8568MDS
-
-config SYS_BOARD
-	default "mpc8568mds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8568MDS"
-
-endif
diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS
deleted file mode 100644
index f4747866d2..0000000000
--- a/board/freescale/mpc8568mds/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8568MDS BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8568mds/
-F:	include/configs/MPC8568MDS.h
-F:	configs/MPC8568MDS_defconfig
diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile
deleted file mode 100644
index 1e9095bddd..0000000000
--- a/board/freescale/mpc8568mds/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2004-2007 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= mpc8568mds.o
-obj-y	+= bcsr.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c
deleted file mode 100644
index b1e638af5a..0000000000
--- a/board/freescale/mpc8568mds/bcsr.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007 Freescale Semiconductor.
- */
-
-#include <common.h>
-#include <flash.h>
-#include <asm/io.h>
-
-#include "bcsr.h"
-
-void enable_8568mds_duart(void)
-{
-	volatile uint* duart_mux	= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
-	volatile uint* devices		= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
-	volatile u8 *bcsr		= (u8 *)(CONFIG_SYS_BCSR);
-
-	*duart_mux = 0x80000000;	/* Set the mux to Duart on PMUXCR */
-	*devices  = 0;			/* Enable all peripheral devices */
-	bcsr[5] |= 0x01;		/* Enable Duart in BCSR*/
-}
-
-void enable_8568mds_flash_write(void)
-{
-	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
-
-	bcsr[9] |= 0x01;
-}
-
-void disable_8568mds_flash_write(void)
-{
-	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
-
-	bcsr[9] &= ~(0x01);
-}
-
-void enable_8568mds_qe_mdio(void)
-{
-	u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
-
-	bcsr[7] |= 0x01;
-}
-
-#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
-void reset_8568mds_uccs(void)
-{
-	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
-
-	/* Turn off UCC1 & UCC2 */
-	out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
-	out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN);
-
-	/* Mode is RGMII, all bits clear */
-	out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK |
-					     BCSR_UCC2_MODE_MSK));
-
-	/* Turn UCC1 & UCC2 on */
-	out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN);
-	out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN);
-}
-#endif
diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h
deleted file mode 100644
index a8e13a2a55..0000000000
--- a/board/freescale/mpc8568mds/bcsr.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007 Freescale Semiconductor.
- */
-
-#ifndef __BCSR_H_
-#define __BCSR_H_
-
-#include <common.h>
-
-/* BCSR Bit definitions
-	* BCSR 0 *
-	0:3	ccb sys pll
-	4:6	cfg core pll
-	7	cfg boot seq
-
-	* BCSR 1 *
-	0:2	cfg rom lock
-	3:5	cfg host agent
-	6	PCI IO
-	7	cfg RIO size
-
-	* BCSR 2 *
-	0:4	QE PLL
-	5	QE clock
-	6	cfg PCI arbiter
-
-	* BCSR 3 *
-	0	TSEC1 reduce
-	1	TSEC2 reduce
-	2:3	TSEC1 protocol
-	4:5	TSEC2 protocol
-	6	PHY1 slave
-	7	PHY2 slave
-
-	* BCSR 4 *
-	4	clock enable
-	5	boot EPROM
-	6	GETH transactive reset
-	7	BRD write potect
-
-	* BCSR 5 *
-	1:3	Leds 1-3
-	4	UPC1 enable
-	5	UPC2 enable
-	6	UPC2 pos
-	7	RS232 enable
-
-	* BCSR 6 *
-	0	CFG ver 0
-	1	CFG ver 1
-	6	Register config led
-	7	Power on reset
-
-	* BCSR 7 *
-	2	board host mode indication
-	5	enable TSEC1 PHY
-	6	enable TSEC2 PHY
-
-	* BCSR 8 *
-	0	UCC GETH1 enable
-	1	UCC GMII enable
-	3	UCC TBI enable
-	5	UCC MII enable
-	7	Real time clock reset
-
-	* BCSR 9 *
-	0	UCC2 GETH enable
-	1	UCC2 GMII enable
-	3	UCC2 TBI enable
-	5	UCC2 MII enable
-	6	Ready only - indicate flash ready after burning
-	7	Flash write protect
-*/
-
-#define BCSR_UCC1_GETH_EN	(0x1 << 7)
-#define BCSR_UCC2_GETH_EN	(0x1 << 7)
-#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
-#define BCSR_UCC2_MODE_MSK	(0x3 << 0)
-
-/*BCSR Utils functions*/
-
-void enable_8568mds_duart(void);
-void enable_8568mds_flash_write(void);
-void disable_8568mds_flash_write(void);
-void enable_8568mds_qe_mdio(void);
-
-#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
-void reset_8568mds_uccs(void);
-#endif
-
-#endif	/* __BCSR_H_ */
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
deleted file mode 100644
index 58a979dbc7..0000000000
--- a/board/freescale/mpc8568mds/ddr.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 6;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
deleted file mode 100644
index c04c36b5d8..0000000000
--- a/board/freescale/mpc8568mds/law.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
- *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                512MB
- *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
- *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
- *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
- *4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
- *5)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
- *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
- *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
- *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
- *6.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
- *6.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
- *
- *Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- */
-
-struct law_entry law_table[] = {
-	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
deleted file mode 100644
index 7b379464cd..0000000000
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ /dev/null
@@ -1,359 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <flash.h>
-#include <init.h>
-#include <log.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <ioports.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-#include "bcsr.h"
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* GETH1 */
-	{4, 10, 1, 0, 2}, /* TxD0 */
-	{4,  9, 1, 0, 2}, /* TxD1 */
-	{4,  8, 1, 0, 2}, /* TxD2 */
-	{4,  7, 1, 0, 2}, /* TxD3 */
-	{4, 23, 1, 0, 2}, /* TxD4 */
-	{4, 22, 1, 0, 2}, /* TxD5 */
-	{4, 21, 1, 0, 2}, /* TxD6 */
-	{4, 20, 1, 0, 2}, /* TxD7 */
-	{4, 15, 2, 0, 2}, /* RxD0 */
-	{4, 14, 2, 0, 2}, /* RxD1 */
-	{4, 13, 2, 0, 2}, /* RxD2 */
-	{4, 12, 2, 0, 2}, /* RxD3 */
-	{4, 29, 2, 0, 2}, /* RxD4 */
-	{4, 28, 2, 0, 2}, /* RxD5 */
-	{4, 27, 2, 0, 2}, /* RxD6 */
-	{4, 26, 2, 0, 2}, /* RxD7 */
-	{4, 11, 1, 0, 2}, /* TX_EN */
-	{4, 24, 1, 0, 2}, /* TX_ER */
-	{4, 16, 2, 0, 2}, /* RX_DV */
-	{4, 30, 2, 0, 2}, /* RX_ER */
-	{4, 17, 2, 0, 2}, /* RX_CLK */
-	{4, 19, 1, 0, 2}, /* GTX_CLK */
-	{1, 31, 2, 0, 3}, /* GTX125 */
-
-	/* GETH2 */
-	{5, 10, 1, 0, 2}, /* TxD0 */
-	{5,  9, 1, 0, 2}, /* TxD1 */
-	{5,  8, 1, 0, 2}, /* TxD2 */
-	{5,  7, 1, 0, 2}, /* TxD3 */
-	{5, 23, 1, 0, 2}, /* TxD4 */
-	{5, 22, 1, 0, 2}, /* TxD5 */
-	{5, 21, 1, 0, 2}, /* TxD6 */
-	{5, 20, 1, 0, 2}, /* TxD7 */
-	{5, 15, 2, 0, 2}, /* RxD0 */
-	{5, 14, 2, 0, 2}, /* RxD1 */
-	{5, 13, 2, 0, 2}, /* RxD2 */
-	{5, 12, 2, 0, 2}, /* RxD3 */
-	{5, 29, 2, 0, 2}, /* RxD4 */
-	{5, 28, 2, 0, 2}, /* RxD5 */
-	{5, 27, 2, 0, 3}, /* RxD6 */
-	{5, 26, 2, 0, 2}, /* RxD7 */
-	{5, 11, 1, 0, 2}, /* TX_EN */
-	{5, 24, 1, 0, 2}, /* TX_ER */
-	{5, 16, 2, 0, 2}, /* RX_DV */
-	{5, 30, 2, 0, 2}, /* RX_ER */
-	{5, 17, 2, 0, 2}, /* RX_CLK */
-	{5, 19, 1, 0, 2}, /* GTX_CLK */
-	{1, 31, 2, 0, 3}, /* GTX125 */
-	{4,  6, 3, 0, 2}, /* MDIO */
-	{4,  5, 1, 0, 2}, /* MDC */
-
-	/* UART1 */
-	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
-	{2, 1, 1, 0, 2}, /* UART_RTS1 */
-	{2, 2, 2, 0, 2}, /* UART_CTS1 */
-	{2, 3, 2, 0, 2}, /* UART_SIN1 */
-
-	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-void local_bus_init(void);
-
-int board_early_init_f (void)
-{
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init ();
-
-	enable_8568mds_duart();
-	enable_8568mds_flash_write();
-#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
-	reset_8568mds_uccs();
-#endif
-#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
-	enable_8568mds_qe_mdio();
-#endif
-
-#ifdef CONFIG_SYS_I2C2_OFFSET
-	/* Enable I2C2_SCL and I2C2_SDA */
-	volatile struct par_io *port_c;
-	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
-	port_c->cpdir2 |= 0x0f000000;
-	port_c->cppar2 &= ~0x0f000000;
-	port_c->cppar2 |= 0x0a000000;
-#endif
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	printf ("Board: 8568 MDS\n");
-
-	return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	uint clkdiv;
-	sys_info_t sysinfo;
-
-	get_sys_info(&sysinfo);
-	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
-
-	gur->lbiuiplldcr1 = 0x00078080;
-	if (clkdiv == 16) {
-		gur->lbiuiplldcr0 = 0x7c0f1bf0;
-	} else if (clkdiv == 8) {
-		gur->lbiuiplldcr0 = 0x6c0f1bf0;
-	} else if (clkdiv == 4) {
-		gur->lbiuiplldcr0 = 0x5c0f1bf0;
-	}
-
-	lbc->lcrr |= 0x00030000;
-
-	asm("sync;isync;msync");
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-
-	uint idx;
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-	uint lsdmr_common;
-
-	puts("LBC SDRAM: ");
-	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
-		   "\n       ");
-
-	/*
-	 * Setup SDRAM Base and Option Registers
-	 */
-	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	asm("msync");
-
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	asm("msync");
-
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	asm("msync");
-
-	/*
-	 * MPC8568 uses "new" 15-16 style addressing.
-	 */
-	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
-	lsdmr_common |= LSDMR_BSMA1516;
-
-	/*
-	 * Issue PRECHARGE ALL command.
-	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	/*
-	 * Issue 8 AUTO REFRESH commands.
-	 */
-	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
-		asm("sync;msync");
-		*sdram_addr = 0xff;
-		ppcDcbf((unsigned long) sdram_addr);
-		udelay(100);
-	}
-
-	/*
-	 * Issue 8 MODE-set command.
-	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	/*
-	 * Issue NORMAL OP command.
-	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
-
-#endif	/* enable SDRAM init */
-}
-
-#if defined(CONFIG_PCI)
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8568mds_config_table[] = {
-	{
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 pci_cfgfunc_config_device,
-	 {PCI_ENET0_IOADDR,
-	  PCI_ENET0_MEMADDR,
-	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
-	 },
-	{}
-};
-#endif
-
-static struct pci_controller pci1_hose;
-#endif	/* CONFIG_PCI */
-
-/*
- * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
- */
-void
-pib_init(void)
-{
-	u8 val8, orig_i2c_bus;
-	/*
-	 * Assign PIB PMC2/3 to PCI bus
-	 */
-
-	/*switch temporarily to I2C bus #2 */
-	orig_i2c_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	val8 = 0x00;
-	i2c_write(0x23, 0x6, 1, &val8, 1);
-	i2c_write(0x23, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x23, 0x2, 1, &val8, 1);
-	i2c_write(0x23, 0x3, 1, &val8, 1);
-
-	val8 = 0x00;
-	i2c_write(0x26, 0x6, 1, &val8, 1);
-	val8 = 0x34;
-	i2c_write(0x26, 0x7, 1, &val8, 1);
-	val8 = 0xf9;
-	i2c_write(0x26, 0x2, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x26, 0x3, 1, &val8, 1);
-
-	val8 = 0x00;
-	i2c_write(0x27, 0x6, 1, &val8, 1);
-	i2c_write(0x27, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x27, 0x2, 1, &val8, 1);
-	val8 = 0xef;
-	i2c_write(0x27, 0x3, 1, &val8, 1);
-
-	asm("eieio");
-	i2c_set_bus_num(orig_i2c_bus);
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	int first_free_busno = 0;
-#ifdef CONFIG_PCI1
-	struct fsl_pci_info pci_info;
-	u32 devdisr, pordevsr, io_sel;
-	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	porpllsr = in_be32(&gur->porpllsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug("   %s: devdisr=%x, io_sel=%x\n", __func__, devdisr, io_sel);
-
-	pci_speed = 66666000;
-	pci_32 = 1;
-	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
-	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
-			(pci_32) ? 32 : 64,
-			(pci_speed == 33333000) ? "33" :
-			(pci_speed == 66666000) ? "66" : "unknown",
-			pci_clk_sel ? "sync" : "async",
-			pci_agent ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info.regs);
-
-#ifndef CONFIG_PCI_PNP
-		pci1_hose.config_table = pci_mpc8568mds_config_table;
-#endif
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-
-	fsl_pcie_init_board(first_free_busno);
-}
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
deleted file mode 100644
index fea1606a1d..0000000000
--- a/board/freescale/mpc8568mds/tlb.c
+++ /dev/null
@@ -1,83 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 Initializations */
-	/*
-	 * TLBe 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH (upper half)
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_16M, 1),
-
-	/*
-	 * TLBe 1:	16M	Non-cacheable, guarded
-	 * 0xfe000000	16M	FLASH (lower half)
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/*
-	 * TLBe 2:	1G	Non-cacheable, guarded
-	 * 0x80000000	512M	PCI1 MEM
-	 * 0xa0000000	512M	PCIe MEM
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_1G, 1),
-
-	/*
-	 * TLBe 3:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	8M	PCI1 IO
-	 * 0xe280_0000	8M	PCIe IO
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLBe 4:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 4, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLBe 5:	256K	Non-cacheable, guarded
-	 * 0xf8000000	32K BCSR
-	 * 0xf8008000	32K PIB (CS4)
-	 * 0xf8010000	32K PIB (CS5)
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256K, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS
index 471ea07d3c..df1f0bed93 100644
--- a/board/freescale/t102xrdb/MAINTAINERS
+++ b/board/freescale/t102xrdb/MAINTAINERS
@@ -7,8 +7,3 @@ F:	configs/T1024RDB_defconfig
 F:	configs/T1024RDB_NAND_defconfig
 F:	configs/T1024RDB_SDCARD_defconfig
 F:	configs/T1024RDB_SPIFLASH_defconfig
-F:	configs/T1024RDB_SECURE_BOOT_defconfig
-F:	configs/T1023RDB_defconfig
-F:	configs/T1023RDB_NAND_defconfig
-F:	configs/T1023RDB_SDCARD_defconfig
-F:	configs/T1023RDB_SPIFLASH_defconfig
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
index a94a57e7fe..542e574fed 100644
--- a/board/freescale/t4rdb/Kconfig
+++ b/board/freescale/t4rdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T4160RDB || TARGET_T4240RDB
+if TARGET_T4240RDB
 
 config SYS_BOARD
 	default "t4rdb"
diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS
index 7380408aae..844a15259c 100644
--- a/board/freescale/t4rdb/MAINTAINERS
+++ b/board/freescale/t4rdb/MAINTAINERS
@@ -3,6 +3,5 @@ M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/t4rdb/
 F:	include/configs/T4240RDB.h
-F:	configs/T4160RDB_defconfig
 F:	configs/T4240RDB_defconfig
 F:	configs/T4240RDB_SDCARD_defconfig
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 209983a24b..f1fd623339 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -7,7 +7,6 @@
 ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 else
-obj-$(CONFIG_TARGET_T4160RDB)	+= t4240rdb.o
 obj-$(CONFIG_TARGET_T4240RDB)	+= t4240rdb.o
 obj-y			+= cpld.o
 obj-y			+= eth.o
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index 3a6c63b774..7dd8213ab5 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -132,7 +132,6 @@ config SYS_IVM_EEPROM_PAGE_LEN
 
 source "board/keymile/km83xx/Kconfig"
 source "board/keymile/kmcent2/Kconfig"
-source "board/keymile/kmp204x/Kconfig"
 source "board/keymile/km_arm/Kconfig"
 source "board/keymile/pg-wcom-ls102xa/Kconfig"
 
diff --git a/board/keymile/kmp204x/Kconfig b/board/keymile/kmp204x/Kconfig
deleted file mode 100644
index f74d4295c7..0000000000
--- a/board/keymile/kmp204x/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-if TARGET_KMP204X
-
-config SYS_BOARD
-	default "kmp204x"
-
-config SYS_VENDOR
-	default "keymile"
-
-config SYS_CONFIG_NAME
-	default "kmp204x"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select ARCH_P2041
-	select FSL_DDR_INTERACTIVE
-	select PHYS_64BIT
-	imply CMD_CRAMFS
-	imply FS_CRAMFS
-
-endif
diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS
deleted file mode 100644
index 8b9afffdc7..0000000000
--- a/board/keymile/kmp204x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KMP204X BOARD
-M:	Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
-S:	Maintained
-F:	board/keymile/kmp204x/
-F:	include/configs/kmp204x.h
-F:	configs/kmcoge4_defconfig
diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile
deleted file mode 100644
index 5523ee99aa..0000000000
--- a/board/keymile/kmp204x/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-
-obj-y	:= kmp204x.o ddr.o eth.o tlb.o pci.o law.o ../common/common.o\
-		../common/ivm.o ../common/qrio.o
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
deleted file mode 100644
index 77a00c55c9..0000000000
--- a/board/keymile/kmp204x/ddr.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	if (ctrl_num) {
-		printf("Wrong parameter for controller number %d", ctrl_num);
-		return;
-	}
-
-	/* automatic calibration for nb of cycles between read and DQS pre */
-	popts->cpo_override = 0xFF;
-
-	/* 1/2 clk delay between wr command and data strobe */
-	popts->write_data_delay = 4;
-	/* clk lauched 1/2 applied cylcle after address command */
-	popts->clk_adjust = 4;
-	/* 1T timing: command/address held for only 1 cycle */
-	popts->twot_en = 0;
-
-	/* we have only one module, half str should be OK */
-	popts->half_strength_driver_enable = 1;
-
-	/* wrlvl values overridden as recommended by ddr init func */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-	popts->wrlvl_start = 0x6;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
-}
-
-int dram_init(void)
-{
-	phys_size_t dram_size = 0;
-
-	puts("Initializing with SPD\n");
-
-	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	debug("    DDR: ");
-	gd->ram_size = dram_size;
-
-	return 0;
-}
diff --git a/board/keymile/kmp204x/eth.c b/board/keymile/kmp204x/eth.c
deleted file mode 100644
index 29c5b339ae..0000000000
--- a/board/keymile/kmp204x/eth.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <phy.h>
-
-int board_eth_init(struct bd_info *bis)
-{
-	int ret = 0;
-#ifdef CONFIG_FMAN_ENET
-	struct fsl_pq_mdio_info dtsec_mdio_info;
-
-	printf("Initializing Fman\n");
-
-	dtsec_mdio_info.regs =
-		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the real 1G MDIO bus */
-	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
-	/* DTESC1/2 don't have a PHY, they are temporarily disabled
-	 * so that u-boot doesn't try to unsuccessfuly enable them */
-	fm_disable_port(FM1_DTSEC1);
-	fm_disable_port(FM1_DTSEC2);
-
-	/*
-	 * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
-	 * This is the debug interface, the only one used in u-boot
-	 */
-	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
-	fm_info_set_mdio(FM1_DTSEC5,
-			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-
-	ret = cpu_eth_init(bis);
-
-	/* reenable DTSEC1/2 for later (kernel) */
-	fm_enable_port(FM1_DTSEC1);
-	fm_enable_port(FM1_DTSEC2);
-#endif
-
-	return ret;
-}
-
-#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
-
-#define mv88E1118_PAGE_REG	22
-
-int board_phy_config(struct phy_device *phydev)
-{
-	if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
-		/* driver config is good */
-		if (phydev->drv->config)
-			phydev->drv->config(phydev);
-
-		/* but we still need to fix the LEDs */
-		phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
-		phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
-		phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
-	}
-
-	return 0;
-}
-#endif
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
deleted file mode 100644
index 29dde7a802..0000000000
--- a/board/keymile/kmp204x/kmp204x.c
+++ /dev/null
@@ -1,265 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2011,2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-#include "../common/common.h"
-#include "../common/qrio.h"
-#include "kmp204x.h"
-
-static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
-
-int checkboard(void)
-{
-	printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME);
-
-	return 0;
-}
-
-#define ZL30158_RST	8
-#define BFTIC4_RST	0
-#define RSTRQSR1_WDT_RR	0x00200000
-#define RSTRQSR1_SW_RR	0x00100000
-
-int board_early_init_f(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	bool cpuwd_flag = false;
-
-	/* configure mode for uP reset request */
-	qrio_uprstreq(UPREQ_CORE_RST);
-
-	/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
-	setbits_be32(&gur->ddrclkdr, 0x001f000f);
-
-	/* set reset reason according CPU register */
-	if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
-	    RSTRQSR1_WDT_RR)
-		cpuwd_flag = true;
-
-	qrio_cpuwd_flag(cpuwd_flag);
-	/* clear CPU bits by writing 1 */
-	setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
-
-	/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
-	qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
-	/* and enable WD on it */
-	qrio_wdmask(BFTIC4_RST, true);
-
-	/* set the ZL30138's prstcfg to reset at power-up only */
-	qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
-	/* and take it out of reset as soon as possible (needed for Hooper) */
-	qrio_prst(ZL30158_RST, false, false);
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	int ret = 0;
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	set_liodns();
-	setup_qbman_portals();
-
-	ret = trigger_fpga_config();
-	if (ret)
-		printf("error triggering PCIe FPGA config\n");
-
-	/* enable the Unit LED (red) & Boot LED (on) */
-	qrio_set_leds();
-
-	/* enable Application Buffer */
-	qrio_enable_app_buffer();
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(unsigned long dummy)
-{
-	return 66666666;
-}
-
-#define ETH_FRONT_PHY_RST	15
-#define QSFP2_RST		11
-#define QSFP1_RST		10
-#define ZL30343_RST		9
-
-int misc_init_f(void)
-{
-	/* configure QRIO pis for i2c deblocking */
-	i2c_deblock_gpio_cfg();
-
-	/* configure the front phy's prstcfg and take it out of reset */
-	qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
-	qrio_prst(ETH_FRONT_PHY_RST, false, false);
-
-	/* set the ZL30343 prstcfg to reset at power-up only */
-	qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
-	/* and enable the WD on it */
-	qrio_wdmask(ZL30343_RST, true);
-
-	/* set the QSFPs' prstcfg to reset at power-up and unit rst only */
-	qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
-	qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
-
-	/* and enable the WD on them */
-	qrio_wdmask(QSFP1_RST, true);
-	qrio_wdmask(QSFP2_RST, true);
-
-	return 0;
-}
-
-#define NUM_SRDS_BANKS	2
-
-int misc_init_r(void)
-{
-	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
-		SRDS_PLLCR0_RFCK_SEL_125};
-	unsigned int i;
-
-	/* check SERDES reference clocks */
-	for (i = 0; i < NUM_SRDS_BANKS; i++) {
-		u32 actual = in_be32(&regs->bank[i].pllcr0);
-		actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
-		if (actual != expected[i]) {
-			printf("Warning: SERDES bank %u expects reference \
-			       clock %sMHz, but actual is %sMHz\n", i + 1,
-			       serdes_clock_to_string(expected[i]),
-			       serdes_clock_to_string(actual));
-		}
-	}
-
-	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
-			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
-	return 0;
-}
-
-#if defined(CONFIG_HUSH_INIT_VAR)
-int hush_init_var(void)
-{
-	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_LAST_STAGE_INIT)
-
-int last_stage_init(void)
-{
-#if defined(CONFIG_KMCOGE4)
-	/* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
-	struct bfticu_iomap *bftic4 =
-		(struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
-	u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
-
-	if (dip_switch != 0) {
-		/* start bootloader */
-		puts("DIP:   Enabled\n");
-		env_set("actual_bank", "0");
-	}
-#endif
-	set_km_env();
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-void fdt_fixup_fman_mac_addresses(void *blob)
-{
-	int node, i, ret;
-	char *tmp, *end;
-	unsigned char mac_addr[6];
-
-	/* get the mac addr from env */
-	tmp = env_get("ethaddr");
-	if (!tmp) {
-		printf("ethaddr env variable not defined\n");
-		return;
-	}
-	for (i = 0; i < 6; i++) {
-		mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
-		if (tmp)
-			tmp = (*end) ? end+1 : end;
-	}
-
-	/* find the correct fdt ethernet path and correct it */
-	node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
-	if (node < 0) {
-		printf("no /soc/fman/ethernet path offset\n");
-		return;
-	}
-	ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
-	if (ret) {
-		printf("error setting local-mac-address property\n");
-		return;
-	}
-}
-#endif
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-#ifdef CONFIG_SYS_DPAA_FMAN
-	fdt_fixup_fman_ethernet(blob);
-	fdt_fixup_fman_mac_addresses(blob);
-#endif
-
-	return 0;
-}
-
-#if defined(CONFIG_POST)
-
-/* DIC26_SELFTEST GPIO used to start factory test sw */
-#define SELFTEST_PORT	QRIO_GPIO_A
-#define SELFTEST_PIN	31
-
-int post_hotkeys_pressed(void)
-{
-	qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
-	return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
-}
-#endif
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h
deleted file mode 100644
index 3b858a5571..0000000000
--- a/board/keymile/kmp204x/kmp204x.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- */
-
-
-void pci_of_setup(void *blob, struct bd_info *bd);
diff --git a/board/keymile/kmp204x/law.c b/board/keymile/kmp204x/law.c
deleted file mode 100644
index 2d83dfea15..0000000000
--- a/board/keymile/kmp204x/law.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-#endif
-	SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
-	SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#endif
-#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
-	SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg
deleted file mode 100644
index 3fdfb47ab2..0000000000
--- a/board/keymile/kmp204x/pbi.cfg
+++ /dev/null
@@ -1,74 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-# Refer docs/README.pblimage for more details about how-to configure
-# and create PBL boot image
-#
-
-#PBI commands
-#Configure ALTCBAR for DCSR -> DCSR@89000000
-091380c0 000009C4
-09000010 00000000
-091380c0 000009C4
-09000014 00000000
-091380c0 000009C4
-09000018 81d00000
-#Workaround for A-004849
-091380c0 000009C4
-890B0050 00000002
-091380c0 000009C4
-890B0054 00000002
-091380c0 000009C4
-890B0058 00000002
-091380c0 000009C4
-890B005C 00000002
-091380c0 000009C4
-890B0090 00000002
-091380c0 000009C4
-890B0094 00000002
-091380c0 000009C4
-890B0098 00000002
-091380c0 000009C4
-890B009C 00000002
-091380c0 000009C4
-890B0108 00000012
-091380c0 000009C4
-#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
-89021008 0000f000
-091380c0 000009C4
-89021028 0000f000
-091380c0 000009C4
-89021048 0000f000
-091380c0 000009C4
-89021068 0000f000
-091380c0 000009C4
-#Flush PBL data
-09138000 00000000
-#Disable ALTCBAR
-09000018 00000000
-091380c0 000009C4
-#Initialize CPC1 as 1MB SRAM
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-09010100 00000000
-09010104 fff0000b
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff00000
-09000d08 81000013
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Initialize eSPI controller, default configuration is slow for eSPI to
-#load data, this configuration comes from u-boot eSPI driver.
-09110000 80000403
-09110020 27170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c
deleted file mode 100644
index cdb498da03..0000000000
--- a/board/keymile/kmp204x/pci.c
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-#include <linux/errno.h>
-
-#include "../common/qrio.h"
-#include "kmp204x.h"
-
-#define PROM_SEL_L	11
-/* control the PROM_SEL_L signal*/
-static void toggle_fpga_eeprom_bus(bool cpu_own)
-{
-	qrio_gpio_direction_output(QRIO_GPIO_A, PROM_SEL_L, !cpu_own);
-}
-
-#define CONF_SEL_L	10
-#define FPGA_PROG_L	19
-#define FPGA_DONE	18
-#define FPGA_INIT_L	17
-
-int trigger_fpga_config(void)
-{
-	int ret = 0, init_l;
-	/* approx 10ms */
-	u32 timeout = 10000;
-
-	/* make sure the FPGA_can access the EEPROM */
-	toggle_fpga_eeprom_bus(false);
-
-	/* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
-	qrio_gpio_direction_output(QRIO_GPIO_A, CONF_SEL_L, 0);
-
-	/* trigger the config start */
-	qrio_gpio_direction_output(QRIO_GPIO_A, FPGA_PROG_L, 0);
-
-	/* small delay for INIT_L line */
-	udelay(10);
-
-	/* wait for FPGA_INIT to be asserted */
-	do {
-		init_l = qrio_get_gpio(QRIO_GPIO_A, FPGA_INIT_L);
-		if (timeout-- == 0) {
-			printf("FPGA_INIT timeout\n");
-			ret = -EFAULT;
-			break;
-		}
-		udelay(10);
-	} while (init_l);
-
-	/* deassert FPGA_PROG, config should start */
-	qrio_set_gpio(QRIO_GPIO_A, FPGA_PROG_L, 1);
-
-	return ret;
-}
-
-/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
-static int wait_for_fpga_config(void)
-{
-	int ret = 0, done;
-	/* approx 5 s */
-	u32 timeout = 500000;
-
-	printf("PCIe FPGA config:");
-	do {
-		done = qrio_get_gpio(QRIO_GPIO_A, FPGA_DONE);
-		if (timeout-- == 0) {
-			printf(" FPGA_DONE timeout\n");
-			ret = -EFAULT;
-			goto err_out;
-		}
-		udelay(10);
-	} while (!done);
-
-	printf(" done\n");
-
-err_out:
-	/* deactive CONF_SEL and give the CPU conf EEPROM access */
-	qrio_set_gpio(QRIO_GPIO_A, CONF_SEL_L, 1);
-	toggle_fpga_eeprom_bus(true);
-
-	return ret;
-}
-
-#define PCIE_SW_RST	14
-#define PEXHC_RST	13
-#define HOOPER_RST	12
-
-void pci_init_board(void)
-{
-	qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
-	qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
-	qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
-
-	/* wait for the PCIe FPGA to be configured
-	 * it has been triggered earlier in board_early_init_r */
-	if (wait_for_fpga_config())
-		printf("error finishing PCIe FPGA config\n");
-
-	qrio_prst(PCIE_SW_RST, false, false);
-	qrio_prst(PEXHC_RST, false, false);
-	qrio_prst(HOOPER_RST, false, false);
-	/* Hooper is not direcly PCIe capable */
-	mdelay(50);
-
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/keymile/kmp204x/rcw_kmp204x.cfg b/board/keymile/kmp204x/rcw_kmp204x.cfg
deleted file mode 100644
index 236d5138bc..0000000000
--- a/board/keymile/kmp204x/rcw_kmp204x.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for kmp204x boards
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-14600000 00000000 28200000 00000000
-148E70CF CFC02000 58000000 41000000
-00000000 00000000 00000000 F0428816
-00000000 00000000 00000000 00000000
diff --git a/board/keymile/kmp204x/tlb.c b/board/keymile/kmp204x/tlb.c
deleted file mode 100644
index a268bd8e95..0000000000
--- a/board/keymile/kmp204x/tlb.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	/* TLB 1 */
-	/* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
-	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-	/* QRIO */
-	SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_64K, 1),
-	/* *I*G* - PCI1 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_512M, 1),
-	/* *I*G* - PCI3 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_512M, 1),
-	/* *I*G* - PCI1&3 I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_128K, 1),
-#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
-	/* LBAPP1 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
-	/* LBAPP2 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_256M, 1),
-#endif
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 9, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 11, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 12, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 13, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	/*
-	 * *I*G - NAND
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for nand.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 16, BOOKE_PAGESZ_32K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c
index 3065461be5..a70166a542 100644
--- a/board/lg/sniper/sniper.c
+++ b/board/lg/sniper/sniper.c
@@ -43,6 +43,7 @@ U_BOOT_DRVINFO(sniper_serial) = {
 	.plat = &serial_omap_plat
 };
 
+#if defined(CONFIG_USB_MUSB_HOST) || defined(CONFIG_USB_MUSB_GADGET)
 static struct musb_hdrc_config musb_config = {
 	.multipoint = 1,
 	.dyn_fifo = 1,
@@ -61,6 +62,7 @@ static struct musb_hdrc_platform_data musb_platform_data = {
 	.platform_ops = &omap2430_ops,
 	.board_data = &musb_board_data,
 };
+#endif
 
 void set_muxconf_regs(void)
 {
@@ -147,8 +149,9 @@ int misc_init_r(void)
 	omap_die_id_serial();
 
 	/* MUSB */
-
+#if defined(CONFIG_USB_MUSB_HOST) || defined(CONFIG_USB_MUSB_GADGET)
 	musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE);
+#endif
 
 	return 0;
 }
diff --git a/board/mpc8308_p1m/Kconfig b/board/mpc8308_p1m/Kconfig
deleted file mode 100644
index b7e39dafbc..0000000000
--- a/board/mpc8308_p1m/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MPC8308_P1M
-
-config SYS_BOARD
-	default "mpc8308_p1m"
-
-config SYS_CONFIG_NAME
-	default "mpc8308_p1m"
-
-endif
diff --git a/board/mpc8308_p1m/MAINTAINERS b/board/mpc8308_p1m/MAINTAINERS
deleted file mode 100644
index 80d8de7711..0000000000
--- a/board/mpc8308_p1m/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8308_P1M BOARD
-M:	Ilya Yanok <yanok@emcraft.com>
-S:	Maintained
-F:	board/mpc8308_p1m/
-F:	include/configs/mpc8308_p1m.h
-F:	configs/mpc8308_p1m_defconfig
diff --git a/board/mpc8308_p1m/Makefile b/board/mpc8308_p1m/Makefile
deleted file mode 100644
index 4ec3b0cda9..0000000000
--- a/board/mpc8308_p1m/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010
-# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
-
-obj-y	:= mpc8308_p1m.o sdram.o
diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c
deleted file mode 100644
index 87607bd489..0000000000
--- a/board/mpc8308_p1m/mpc8308_p1m.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <init.h>
-#include <net.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-int checkboard(void)
-{
-	printf("Board: MPC8308 P1M\n");
-
-	return 0;
-}
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	sysconf83xx_t *sysconf = &immr->sysconf;
-	law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *pcie_reg[] = { pcie_regions_0 };
-
-	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
-					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(1, pcie_reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-	fsl_fdt_fixup_dr_usb(blob, bd);
-
-	return 0;
-}
-#endif
-
-int board_eth_init(struct bd_info *bis)
-{
-	int rv, num_if = 0;
-
-	/* Initialize TSECs first */
-	rv = cpu_eth_init(bis);
-	if (rv >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize TSECs.\n");
-
-	rv = pci_eth_init(bis);
-	if (rv >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize PCI Ethernet.\n");
-
-	return num_if;
-}
diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c
deleted file mode 100644
index 62a2d8a53a..0000000000
--- a/board/mpc8308_p1m/sdram.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
- *
- * This files is  mostly identical to the original from
- * board/freescale/mpc8308rdb/sdram.c
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <asm/global_data.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-
-	out_be32(&im->sysconf.ddrlaw[0].bar,
-			CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
-	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
-	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
-
-	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
-	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
-
-	/* Currently we use only one CS, so disable the other bank. */
-	out_be32(&im->ddr.cs_config[1], 0);
-
-	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
-	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
-	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
-	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
-	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-
-	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
-	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
-	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
-	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
-
-	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
-	sync();
-
-	/* enable DDR controller */
-	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
-	sync();
-
-	return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
-}
-
-int dram_init(void)
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize;
-
-	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM */
-	msize = fixed_sdram();
-
-	/* set total bus SDRAM size(bytes)  -- DDR */
-	gd->ram_size = msize;
-
-	return 0;
-}
diff --git a/board/sbc8349/Kconfig b/board/sbc8349/Kconfig
deleted file mode 100644
index 129d6b92ec..0000000000
--- a/board/sbc8349/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SBC8349
-
-config SYS_BOARD
-	default "sbc8349"
-
-config SYS_CONFIG_NAME
-	default "sbc8349"
-
-endif
diff --git a/board/sbc8349/MAINTAINERS b/board/sbc8349/MAINTAINERS
deleted file mode 100644
index af95c1dd0d..0000000000
--- a/board/sbc8349/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-SBC8349 BOARD
-M:	Paul Gortmaker <paul.gortmaker@windriver.com>
-S:	Maintained
-F:	board/sbc8349/
-F:	include/configs/sbc8349.h
-F:	configs/sbc8349_defconfig
-F:	configs/sbc8349_PCI_33_defconfig
-F:	configs/sbc8349_PCI_66_defconfig
diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile
deleted file mode 100644
index c469174085..0000000000
--- a/board/sbc8349/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2006 Wind River Systems, Inc.
-
-obj-y += sbc8349.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/sbc8349/README b/board/sbc8349/README
deleted file mode 100644
index 3c142e0407..0000000000
--- a/board/sbc8349/README
+++ /dev/null
@@ -1,127 +0,0 @@
-
-
-	U-Boot for Wind River SBC834x Boards
-	====================================
-
-
-The Wind River SBC834x board is a 6U form factor (not CPCI) reference
-design that uses the MPC8347E or MPC8349E processor.  U-Boot support
-for this board is heavily based on the existing U-Boot support for
-Freescale MPC8349 reference boards.
-
-Support has been primarily tested on the SBC8349 version of the board,
-although earlier versions were also tested on the SBC8347.  The primary
-difference in the two is the level of PCI functionality.
-
-	http://www.windriver.com/products/OCD/SBC8347E_49E/
-
-
-Flash Details:
-==============
-
-The flash type is intel 28F640Jx (4096x16) [one device].  Base address
-is 0xFF80_0000 which is also where the Hardware Reset Configuration
-Word (HRCW) is stored.  Caution should be used to not reset the
-board without having a valid HRCW in place (i.e. erased flash) as
-then a Wind River ICE will be required to restore the HRCW and flash
-image.
-
-
-Restoring a corrupted or missing flash image:
-=============================================
-
-Note that U-Boot versions up to and including 2009.06 had essentially
-two copies of U-Boot in flash; one at the very beginning, which set
-the HRCW, and one at the very end, which was the image that was run.
-As of this point in time, the two have been combined into just one
-at the beginning of flash, which provides both the HRCW, and the image
-that is executed.  This frees up the remainder of flash for other uses.
-Use of the U-Boot command "fli" will indicate what parts are in use.
-Details for storing U-Boot to flash using a Wind River ICE can be found
-on page 19 of the board manual (request ERG-00328-001).  The following
-is a summary of that information:
-
-  - Connect ICE and establish connection to it from WorkBench/OCD.
-  - Ensure you have background mode (BKM) in the OCD terminal window.
-  - Select the appropriate flash type (listed above)
-  - Prepare a U-Boot image by using the Wind River Convert utility;
-    by using "Convert and Add file" on the ELF file from your build.
-    Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
-    trying to preserve your old environment settings and user flash).
-  - Set the start address of the erase/flash process to FF80_0000
-  - Set the target RAM required to 64kB.
-  - Select sectors for erasing (see note on environment below)
-  - Select Erase and Reprogram.
-
-Note that some versions of the register files used with Workbench
-would zero some TSEC registers, which inhibits ethernet operation
-by U-Boot when this register file is played to the target.  Using
-"INN" in the OCD terminal window instead of "IN" before the "GO"
-will not play the register file, and allow U-Boot to use the TSEC
-interface while executed from the ICE "GO" command.
-
-Alternatively, you can locate the register file which will be named
-WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines
-beginning with "SCGA TSEC1" and "SCGA TSEC2".  This allows you to
-use all the remaining register file content.
-
-If you wish to preserve your prior U-Boot environment settings,
-then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
-The size for converting (and erasing) must be at least as large
-as u-boot.bin.
-
-
-Updating U-Boot with U-Boot:
-============================
-
-This procedure is very similar to other boards that have U-Boot installed.
-Assuming that the network has been configured, and that the new u-boot.bin
-has been copied to the TFTP server, the commands are:
-
-	tftp 200000 u-boot.bin
-	protect off all
-	erase ff800000 ff83ffff
-	cp.b 200000 ff800000 40000
-	protect on all
-
-You may wish to do a "md ff800000 20" operation as a prefix and postfix
-to the above steps to inspect/compare the HRCW before/after as an extra
-safety check before resetting the board upon completion of the reflash.
-
-PCI:
-====
-
-There are three configuration choices:
-	sbc8349_config
-	sbc8349_PCI_33_config
-	sbc8349_PCI_66_config
-
-The 1st does not enable CONFIG_PCI, and assumes that the PCI slot
-will be left empty (M66EN high), and so the board will operate with
-a base clock of 66MHz.  Note that you need both PCI enabled in U-Boot
-and linux in order to have functional PCI under linux.  The only
-reason for choosing to not enable PCI would be if you had a very
-early (rev 1.0) CPU with possible PCI issues.
-
-The second enables PCI support and builds for a 33MHz clock rate.  Note
-that if a 33MHz 32bit card is inserted in the slot, then the whole board
-will clock down to a 33MHz base clock instead of the default 66MHz.  This
-will change the baud clocks and mess up your serial console output if you
-were previously running at 66MHz.  If you want to use a 33MHz PCI card,
-then you should build a U-Boot with sbc8349_PCI_33_config and store this
-to flash prior to powering down the board and inserting the 33MHz PCI
-card.
-
-The third option builds PCI support in, and leaves the clocking at the
-default 66MHz.  This has been tested with an intel PCI-X e1000 card.
-This is also the appropriate choice for people with a recent (non 1.0)
-CPU who currently have the PCI slot physically empty, but intend to
-possibly add a PCI-X card at a later date.
-
-   => pci
-   Scanning PCI devices on bus 0
-   BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
-   _____________________________________________________________
-   00.00.00   0x1957     0x0080     Processor               0x20
-   00.11.00   0x8086     0x1026     Network controller      0x00
-   =>
diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
deleted file mode 100644
index 26c4f24e4f..0000000000
--- a/board/sbc8349/pci.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * pci.c -- WindRiver SBC8349 PCI board support.
- * Copyright (c) 2006 Wind River Systems, Inc.
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * Based on MPC8349 PCI support but w/o PIB related code.
- */
-
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-/*
- * pci_init_board()
- *
- * NOTICE: PCI2 is not supported. There is only one
- * physical PCI slot on the board.
- *
- */
-void
-pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci1_regions };
-
-	/* Enable all 8 PCI_CLK_OUTPUTS */
-	clk->occr = 0xff000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	udelay(2000);
-
-	mpc83xx_pci_init(1, reg);
-}
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
deleted file mode 100644
index b440a0b17e..0000000000
--- a/board/sbc8349/sbc8349.c
+++ /dev/null
@@ -1,243 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * sbc8349.c -- WindRiver SBC8349 board support.
- * Copyright (c) 2006-2007 Wind River Systems, Inc.
- *
- * Paul Gortmaker <paul.gortmaker@windriver.com>
- * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/bitops.h>
-#include <asm/global_data.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <spd_sdram.h>
-#include <miiphy.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int fixed_sdram(void);
-void sdram_init(void);
-
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
-void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f (void)
-{
-	return 0;
-}
-#endif
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-
-int dram_init(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
-	msize = spd_sdram();
-#else
-	msize = fixed_sdram();
-#endif
-	/*
-	 * Initialize SDRAM if it is on local bus.
-	 */
-	sdram_init();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-	/* set total bus SDRAM size(bytes)  -- DDR */
-	gd->ram_size = msize * 1024 * 1024;
-
-	return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE;
-	u32 ddr_size = msize << 20;	/* DDR size in bytes */
-	u32 ddr_size_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currently any ddr size other than 256 is not supported
-#endif
-
-#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[2].csbnds =
-		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
-				CSBNDS_EA_SHIFT) & CSBNDS_EA);
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-
-	/* currently we use only one CS, so disable the other banks */
-	im->ddr.cs_config[0] = 0;
-	im->ddr.cs_config[1] = 0;
-	im->ddr.cs_config[3] = 0;
-
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
-	im->ddr.sdram_cfg =
-		SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
-		| SDRAM_CFG_2T_EN
-#endif
-		| SDRAM_CFG_SDRAM_TYPE_DDR1;
-#if defined (CONFIG_DDR_32BIT)
-	/* for 32-bit mode burst length is 8 */
-	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	udelay(200);
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	return msize;
-}
-#endif/*!CONFIG_SYS_SPD_EEPROM*/
-
-
-int checkboard (void)
-{
-	puts("Board: Wind River SBC834x\n");
-	return 0;
-}
-
-/*
- * if board is fitted with SDRAM
- */
-#if defined(CONFIG_SYS_BR2_PRELIM)  \
-	&& defined(CONFIG_SYS_OR2_PRELIM) \
-	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
-	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void sdram_init(void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &immap->im_lbc;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-	const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
-				 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
-				 LSDMR_WRC3 | LSDMR_CL3;
-
-	puts("\n   SDRAM on Local Bus: ");
-	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
-	/*
-	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
-	 */
-
-	/* setup mtrpt, lsrt and lbcr for LB bus */
-	lbc->lbcr = 0x00000000;
-	/* LB refresh timer prescal, 266MHz/32 */
-	lbc->mrtpr = 0x20000000;
-	/* LB sdram refresh timer, about 6us */
-	lbc->lsrt = 0x32000000;
-	asm("sync");
-
-	/*
-	 * Configure the SDRAM controller Machine Mode Register.
-	 */
-	/* 0x40636733; normal operation */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
-
-	/* 0x68636733; precharge all the banks */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	/* 0x48636733; auto refresh */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
-	asm("sync");
-	/*1 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*2 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*3 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*4 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*5 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*6 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*7 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*8 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	/* 0x58636733; mode register write operation */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	/* 0x40636733; normal operation */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-}
-#else
-void sdram_init(void)
-{
-	puts("   SDRAM on Local Bus: Disabled in config\n");
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/sbc8548/Kconfig b/board/sbc8548/Kconfig
deleted file mode 100644
index 626cbdf2ab..0000000000
--- a/board/sbc8548/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SBC8548
-
-config SYS_BOARD
-	default "sbc8548"
-
-config SYS_CONFIG_NAME
-	default "sbc8548"
-
-endif
diff --git a/board/sbc8548/MAINTAINERS b/board/sbc8548/MAINTAINERS
deleted file mode 100644
index ba1f2475ea..0000000000
--- a/board/sbc8548/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-SBC8548 BOARD
-M:	Paul Gortmaker <paul.gortmaker@windriver.com>
-S:	Maintained
-F:	board/sbc8548/
-F:	include/configs/sbc8548.h
-F:	configs/sbc8548_defconfig
-F:	configs/sbc8548_PCI_33_defconfig
-F:	configs/sbc8548_PCI_33_PCIE_defconfig
-F:	configs/sbc8548_PCI_66_defconfig
-F:	configs/sbc8548_PCI_66_PCIE_defconfig
diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile
deleted file mode 100644
index 83d208cf1f..0000000000
--- a/board/sbc8548/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2004-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>.
-# Added support for Wind River SBC8548 board
-
-obj-y	+= sbc8548.o
-obj-y	+= law.o
-obj-y	+= tlb.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8548/README b/board/sbc8548/README
deleted file mode 100644
index 0def245bd9..0000000000
--- a/board/sbc8548/README
+++ /dev/null
@@ -1,269 +0,0 @@
-Intro:
-======
-
-The SBC8548 is a stand alone single board computer with a 1GHz
-MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
-memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
-and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
-ethernet connections.
-
-U-Boot Configuration:
-=====================
-
-The following possible U-Boot configuration targets are available:
-
-	1) sbc8548_config
-	2) sbc8548_PCI_33_config
-	3) sbc8548_PCI_66_config
-	4) sbc8548_PCI_33_PCIE_config
-	5) sbc8548_PCI_66_PCIE_config
-
-Generally speaking, most people should choose to use #5.  Details
-of each choice are listed below.
-
-Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
-will be left empty (M66EN high), and so the board will operate with
-a base clock of 66MHz.	Note that you need both PCI enabled in U-Boot
-and linux in order to have functional PCI under linux.
-
-The second enables PCI support and builds for a 33MHz clock rate.  Note
-that if a 33MHz 32bit card is inserted in the slot, then the whole board
-will clock down to a 33MHz base clock instead of the default 66MHz.  This
-will change the baud clocks and mess up your serial console output if you
-were previously running at 66MHz.  If you want to use a 33MHz PCI card,
-then you should build a U-Boot with a _PCI_33_ config and store this
-to flash prior to powering down the board and inserting the 33MHz PCI
-card. [The above discussion assumes that the SW2[1-4] has not been changed
-to reflect a different CCB:SYSCLK ratio]
-
-The third option builds PCI support in, and leaves the clocking at the
-default 66MHz.	Options four and five are just repeats of option two
-and three, but with PCI-e support enabled as well.
-
-PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
-is shown below for sbc8548_PCI_66_PCIE_config.	(Note that PCI-e with
-a 33MHz PCI configuration is currently untested.)
-
-    => pci 0
-    Scanning PCI devices on bus 0
-    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
-    _____________________________________________________________
-    00.00.00   0x1057	  0x0012     Processor		     0x20
-    00.01.00   0x8086	  0x1026     Network controller	     0x00
-    => pci 1
-    Scanning PCI devices on bus 1
-    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
-    _____________________________________________________________
-    01.00.00   0x1957	  0x0012     Processor		     0x20
-    => pci 2
-    Scanning PCI devices on bus 2
-    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
-    _____________________________________________________________
-    02.00.00   0x1148	  0x9e00     Network controller	     0x00
-    =>
-
-Memory Size and using SPD:
-==========================
-
-The default configuration uses hard coded memory configuration settings
-for 256MB of DDR2 @400MHz.  It does not by default use the DDR2 SPD
-EEPROM data to read what memory is installed.
-
-There is a hardware errata, which causes the older local bus SDRAM
-SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
-that the SPD data can not be read reliably.  You can test if your
-board has the errata fix by running "i2c probe".  If you see 0x53
-as a valid device, it has been fixed.  If you only see 0x50, 0x51
-then your board does not have the fix.
-
-You can also visually inspect the board to see if this hardware
-fix has been applied:
-
-      1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
-	 the back of the PCB behind the DDR SDRAM SODIMM connector.
-      2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
-	 to R313 pin 2.	 Pin 2 for each resistor is the end of the
-	 resistor closest to the CPU.
-
-Boards without the mod will have R314 and R313 in parallel, like "||".
-After the mod, they will be touching and form an "L" shape.
-
-If you want to upgrade to larger RAM size, you can simply enable
-	#define CONFIG_SPD_EEPROM
-	#define CONFIG_DDR_SPD
-in include/configs/sbc8548.h file.  (The lines are already there
-but listed as #undef).
-
-If you did the i2c test, and your board does not have the errata
-fix, then you will have to physically remove the LBC 128MB DIMM
-from the board's socket to resolve the above i2c address overlap
-issue and allow SPD autodetection of RAM to work.
-
-
-Updating U-Boot with U-Boot:
-============================
-
-Note that versions of U-Boot up to and including 2009.08 had U-Boot stored
-at 0xfff8_0000 -> 0xffff_ffff (512k).  Currently it is being stored from
-0xfffa_0000 -> 0xffff_ffff (384k).  If you use an old macro/script to
-update U-Boot with U-Boot and it uses the old address, you will render
-your board inoperable, and you will require JTAG recovery.
-
-The following steps list how to update with the current address:
-
-	tftp u-boot.bin
-	md 200000 10
-	protect off all
-	erase fffa0000 ffffffff
-	cp.b 200000 fffa0000 60000
-	md fffa0000 10
-	protect on all
-
-The "md" steps in the above are just a precautionary step that allow
-you to confirm the U-Boot version that was downloaded, and then confirm
-that it was copied to flash.
-
-The above assumes that you are using the default board settings which
-have U-Boot in the 8MB flash, tied to /CS0.
-
-If you are running the default 8MB /CS0 settings but want to store an
-image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
-(as a backup, etc) then the steps will become:
-
-	tftp u-boot.bin
-	md 200000 10
-	protect off all
-	era eff00000 efffffff
-	cp.b 200000 eff00000 100000
-	md eff00000 10
-	protect on all
-
-Finally, if you are running the alternate 64MB /CS0 settings and want
-to update the in-use U-Boot image, then (again with CONFIG_SYS_ALT_BOOT
-enabled) the steps will become:
-
-	tftp u-boot.bin
-	md 200000 10
-	protect off all
-	era fff00000 ffffffff
-	cp.b 200000 fff00000 100000
-	md fff00000 10
-	protect on all
-
-
-Hardware Reference:
-===================
-
-The following contains some summary information on hardware settings
-that are relevant to U-Boot, based on the board manual.	 For the
-most up to date and complete details of the board, please request the
-reference manual ERG-00327-001.pdf from www.windriver.com
-
-Boot flash:
-	intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
-
-Sodimm flash:
-	intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
-	Note that this address reflects the default setting for
-	the JTAG debugging tools, but since the alignment is
-	rather inconvenient, U-Boot puts it at 0xec00_0000.
-
-
-	Jumpers:
-
-Jumper		Name		ON		OFF
-----------------------------------------------------------------
-JP12		CS0/CS6 swap	see note[*]	see note[*]
-
-JP13		SODIMM flash	write OK	writes disabled
-		write prot.
-
-JP14		HRESET/TRST	joined		isolated
-
-JP15		PWR ON		when AC pwr	use S1 for on/off
-
-JP16		Demo LEDs	lit		not lit
-
-JP19		PCI mode	PCI		PCI-X
-
-
-[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
-onto /CS0 and the SODIMM flash on /CS6 (default).  When JP12
-is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
-SODIMM flash and /CS6 is for the boot flash.  Note that in this
-alternate setting, you also need to switch SW2.8 to ON.
-See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
-and boot U-Boot from the 64MB SODIMM
-
-
-	Switches:
-
-The defaults are marked with a *
-
-Name		Desc.			ON		OFF
-------------------------------------------------------------------
-S1		Pwr toggle		n/a		n/a
-
-SW2.1		CFG_SYS_PLL0		1		0*
-SW2.2		CFG_SYS_PLL1		1*		0
-SW2.3		CFG_SYS_PLL2		1*		0
-SW2.4		CFG_SYS_PLL3		1		0*
-SW2.5		CFG_CORE_PLL0		1*		0
-SW2.6		CFG_CORE_PLL1		1		0*
-SW2.7		CFG_CORE_PLL2		1*		0
-SW2.8		CFG_ROM_LOC1		1		0*
-
-SW3.1		CFG_HOST_AGT0		1*		0
-SW3.2		CFG_HOST_AGT1		1*		0
-SW3.3		CFG_HOST_AGT2		1*		0
-SW3.4		CFG_IO_PORTS0		1*		0
-SW3.5		CFG_IO_PORTS0		1		0*
-SW3.6		CFG_IO_PORTS0		1		0*
-
-SerDes CLK(MHz)		SW5.1		SW5.2
-----------------------------------------------
-25			0		0
-100*			1		0
-125			0		1
-200			1		1
-
-SerDes CLK spread	SW5.3		SW5.4
-----------------------------------------------
-+/- 0.25%		0		0
--0.50%			1		0
--0.75%			0		1
-No Spread*		1		1
-
-SW4 settings are readable from the EPLD and are currently not used for
-any hardware settings (i.e. user configuration switches).
-
-	LEDs:
-
-Name		Desc.			ON		OFF
-------------------------------------------------------------------
-D13		PCI/PCI-X		PCI-X		PCI
-D14		3.3V PWR		3.3V		no power
-D15		SYSCLK			66MHz		33MHz
-
-
-	Default Memory Map:
-
-start		end		CS<n>	width	Desc.
-----------------------------------------------------------------------
-0000_0000	0fff_ffff	MCS0,1	64	DDR2 (256MB)
-f000_0000	f7ff_ffff	CS3,4	32	LB SDRAM (128MB)
-f800_0000	f8b0_1fff	CS5	-	EPLD
-fb80_0000	ff7f_ffff	CS6	32	SODIMM flash (64MB) [*]
-ff80_0000	ffff_ffff	CS0	8	Boot flash (8MB)
-
-[*] fb80 represents the default programmed by WR JTAG register files,
-    but U-Boot places the flash at either ec00 or fc00 based on JP12.
-
-The EPLD on CS5 demuxes the following devices at the following offsets:
-
-offset		size	width	device
---------------------------------------------------------
-0		1fff	8	7 segment display LED
-10_0000		1fff	4	user switches
-30_0000		1fff	4	HW Rev. register
-b0_0000		1fff	8	8kB EEPROM
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
deleted file mode 100644
index 61bc77c418..0000000000
--- a/board/sbc8548/ddr.c
+++ /dev/null
@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <linux/delay.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
-
-#ifdef CONFIG_SPD_EEPROM
-/*
- * Workaround for hardware errata.  An i2c address conflict
- * existed on earlier boards; the workaround moved the DDR
- * SPD from 0x51 to 0x53.  So we try and read 0x53 1st, and
- * if that fails, then fall back to reading at 0x51.
- */
-void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
-{
-	int ret;
-
-#ifdef ALT_SPD_EEPROM_ADDRESS
-	if (i2c_address == SPD_EEPROM_ADDRESS) {
-		ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
-				sizeof(generic_spd_eeprom_t));
-		if (ret == 0)
-			return;		/* Good data at 0x53 */
-		memset(spd, 0, sizeof(generic_spd_eeprom_t));
-	}
-#endif
-	ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
-				sizeof(generic_spd_eeprom_t));
-	if (ret) {
-		printf("DDR: failed to read SPD from addr %u\n", i2c_address);
-		memset(spd, 0, sizeof(generic_spd_eeprom_t));
-	}
-}
-
-#else
-/*
- *  fixed_sdram init -- doesn't use serial presence detect.
- *  Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
- */
-phys_size_t fixed_sdram(void)
-{
-	struct ccsr_ddr __iomem *ddr =
-		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
-
-	out_be32(&ddr->cs0_bnds,	0x0000007f);
-	out_be32(&ddr->cs1_bnds,	0x008000ff);
-	out_be32(&ddr->cs2_bnds,	0x00000000);
-	out_be32(&ddr->cs3_bnds,	0x00000000);
-
-	out_be32(&ddr->cs0_config,	0x80010101);
-	out_be32(&ddr->cs1_config,	0x80010101);
-	out_be32(&ddr->cs2_config,	0x00000000);
-	out_be32(&ddr->cs3_config,	0x00000000);
-
-	out_be32(&ddr->timing_cfg_3,	0x00000000);
-	out_be32(&ddr->timing_cfg_0,	0x00220802);
-	out_be32(&ddr->timing_cfg_1,	0x38377322);
-	out_be32(&ddr->timing_cfg_2,	0x0fa044C7);
-
-	out_be32(&ddr->sdram_cfg,	0x4300C000);
-	out_be32(&ddr->sdram_cfg_2,	0x24401000);
-
-	out_be32(&ddr->sdram_mode,	0x23C00542);
-	out_be32(&ddr->sdram_mode_2,	0x00000000);
-
-	out_be32(&ddr->sdram_interval,	0x05080100);
-	out_be32(&ddr->sdram_md_cntl,	0x00000000);
-	out_be32(&ddr->sdram_data_init,	0x00000000);
-	out_be32(&ddr->sdram_clk_cntl,	0x03800000);
-	asm("sync;isync;msync");
-	udelay(500);
-
-	#ifdef CONFIG_DDR_ECC
-	  /* Enable ECC checking */
-	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
-	#else
-	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
-	#endif
-
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
deleted file mode 100644
index 97271ea6f6..0000000000
--- a/board/sbc8548/law.c
+++ /dev/null
@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000	0x0fff_ffff	DDR			256M
- * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M
- * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M
- * 0xe000_0000	0xe000_ffff	CCSR			1M
- * 0xe200_0000	0xe27f_ffff	PCI1 IO			8M
- * 0xe280_0000	0xe2ff_ffff	PCIe IO			8M
- * 0xec00_0000	0xefff_ffff	FLASH (2nd bank)	64M
- * 0xf000_0000	0xf7ff_ffff	SDRAM			128M
- * 0xf8b0_0000	0xf80f_ffff	EEPROM			1M
- * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M
- *
- * If swapped CS0/CS6 via JP12+SW2.8:
- * 0xef80_0000	0xefff_ffff	FLASH (2nd bank)	8M
- * 0xfc00_0000	0xffff_ffff	FLASH (boot bank)	64M
- *
- * Notes:
- *	CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *	If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_SYS_ALT_BOOT
-	SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
-#else
-	SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#endif
-#ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
-#endif
-#ifdef CONFIG_SYS_LBC_SDRAM_BASE
-	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#else
-	/* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
-	SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
deleted file mode 100644
index bd4b528d03..0000000000
--- a/board/sbc8548/sbc8548.c
+++ /dev/null
@@ -1,315 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
- *
- * Copyright 2007 Embedded Specialties, Inc.
- *
- * Copyright 2004, 2007 Freescale Semiconductor.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <spd_sdram.h>
-#include <netdev.h>
-#include <tsec.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-void local_bus_init(void);
-
-int board_early_init_f (void)
-{
-	return 0;
-}
-
-int checkboard (void)
-{
-	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
-
-	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
-			in_8(rev) >> 4);
-
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init ();
-
-	out_be32(&ecm->eedr, 0xffffffff);	/* clear ecm errors */
-	out_be32(&ecm->eeer, 0xffffffff);	/* enable ecm errors */
-	return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
-	sys_info_t sysinfo;
-
-	get_sys_info(&sysinfo);
-
-	lbc_mhz = sysinfo.freq_localbus / 1000000;
-	clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
-
-	debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
-
-	out_be32(&gur->lbiuiplldcr1, 0x00078080);
-	if (clkdiv == 16) {
-		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
-	} else if (clkdiv == 8) {
-		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
-	} else if (clkdiv == 4) {
-		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
-	}
-
-	/*
-	 * Local Bus Clock > 83.3 MHz. According to timing
-	 * specifications set LCRR[EADC] to 2 delay cycles.
-	 */
-	if (lbc_mhz > 83) {
-		lcrr &= ~LCRR_EADC;
-		lcrr |= LCRR_EADC_2;
-	}
-
-	/*
-	 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
-	 * disable PLL bypass for Local Bus Clock > 83 MHz.
-	 */
-	if (lbc_mhz >= 66)
-		lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
-
-	else
-		lcrr |= LCRR_DBYP;	/* DLL Bypass */
-
-	out_be32(&lbc->lcrr, lcrr);
-	asm("sync;isync;msync");
-
-	 /*
-	 * According to MPC8548ERMAD Rev.1.3 read back LCRR
-	 * and terminate with isync
-	 */
-	lcrr = in_be32(&lbc->lcrr);
-	asm ("isync;");
-
-	/* let DLL stabilize */
-	udelay(500);
-
-	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
-	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
-
-	uint idx;
-	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-	uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
-
-	puts("    SDRAM: ");
-
-	print_size(size, "\n");
-
-	/*
-	 * Setup SDRAM Base and Option Registers
-	 */
-	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
-	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
-	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
-	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
-
-	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-	asm("msync");
-
-	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
-	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
-	asm("msync");
-
-	/*
-	 * Issue PRECHARGE ALL command.
-	 */
-	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	*sdram_addr2 = 0xff;
-	ppcDcbf((unsigned long) sdram_addr2);
-	udelay(100);
-
-	/*
-	 * Issue 8 AUTO REFRESH commands.
-	 */
-	for (idx = 0; idx < 8; idx++) {
-		out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
-		asm("sync;msync");
-		*sdram_addr = 0xff;
-		ppcDcbf((unsigned long) sdram_addr);
-		*sdram_addr2 = 0xff;
-		ppcDcbf((unsigned long) sdram_addr2);
-		udelay(100);
-	}
-
-	/*
-	 * Issue 8 MODE-set command.
-	 */
-	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	*sdram_addr2 = 0xff;
-	ppcDcbf((unsigned long) sdram_addr2);
-	udelay(100);
-
-	/*
-	 * Issue RFEN command.
-	 */
-	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
-	asm("sync;msync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	*sdram_addr2 = 0xff;
-	ppcDcbf((unsigned long) sdram_addr2);
-	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
-
-#endif	/* enable SDRAM init */
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int
-testdram(void)
-{
-	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
-	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
-	uint *p;
-
-	printf("Testing DRAM from 0x%08x to 0x%08x\n",
-	       CONFIG_SYS_MEMTEST_START,
-	       CONFIG_SYS_MEMTEST_END);
-
-	printf("DRAM test phase 1:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("DRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf("DRAM test phase 2:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("DRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf("DRAM test passed.\n");
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif	/* CONFIG_PCI1 */
-
-#ifdef CONFIG_PCI
-void
-pci_init_board(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	int first_free_busno = 0;
-
-#ifdef CONFIG_PCI1
-	struct fsl_pci_info pci_info;
-	u32 devdisr = in_be32(&gur->devdisr);
-	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 porpllsr = in_be32(&gur->porpllsr);
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
-		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
-		uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-		uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* get_clock_freq() */
-
-		printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
-			(pci_32) ? 32 : 64,
-			(pci_speed == 33000000) ? "33" :
-			(pci_speed == 66000000) ? "66" : "unknown",
-			pci_clk_sel ? "sync" : "async",
-			pci_arb ? "arbiter" : "external-arbiter");
-
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
-
-	fsl_pcie_init_board(first_free_busno);
-}
-#endif
-
-int board_eth_init(struct bd_info *bis)
-{
-	tsec_standard_init(bis);
-	pci_eth_init(bis);
-	return 0;	/* otherwise cpu_eth_init gets run */
-}
-
-int last_stage_init(void)
-{
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_FSL_PCI_INIT
-	FT_FSL_PCI_SETUP;
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
deleted file mode 100644
index 8ad01d10e4..0000000000
--- a/board/sbc8548/tlb.c
+++ /dev/null
@@ -1,121 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/*
-	 * TLB 0:	64M	Non-cacheable, guarded
-	 * 0xfc000000	56M	unused
-	 * 0xff800000	8M	boot FLASH
-	 *	.... or ....
-	 * 0xfc000000	64M	user flash
-	 *
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 1:	1G	Non-cacheable, guarded
-	 * 0x80000000	512M	PCI1 MEM
-	 * 0xa0000000	512M	PCIe MEM
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_1G, 1),
-
-	/*
-	 * TLB 2:	64M	Non-cacheable, guarded
-	 * 0xe0000000	1M	CCSRBAR
-	 * 0xe2000000	8M	PCI1 IO
-	 * 0xe2800000	8M	PCIe IO
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_SYS_LBC_SDRAM_BASE
-	/*
-	 * TLB 3:	64M	Cacheable, non-guarded
-	 * 0xf0000000	64M	LBC SDRAM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 3, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 4:	64M	Cacheable, non-guarded
-	 * 0xf4000000	64M	LBC SDRAM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
-		      CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 4, BOOKE_PAGESZ_64M, 1),
-#endif
-
-	/*
-	 * TLB 5:	16M	Cacheable, non-guarded
-	 * 0xf8000000	1M	7-segment LED display
-	 * 0xf8100000	1M	User switches
-	 * 0xf8300000	1M	Board revision
-	 * 0xf8b00000	1M	EEPROM
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_16M, 1),
-
-#ifndef CONFIG_SYS_ALT_BOOT
-	/*
-	 * TLB 6:	64M	Non-cacheable, guarded
-	 * 0xec000000	64M	64MB user FLASH
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_64M, 1),
-#else
-	/*
-	 * TLB 6:	4M	Non-cacheable, guarded
-	 * 0xef800000	4M	1st 1/2 8MB soldered FLASH
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_4M, 1),
-
-	/*
-	 * TLB 7:	4M	Non-cacheable, guarded
-	 * 0xefc00000	4M	2nd half 8MB soldered FLASH
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
-		      CONFIG_SYS_ALT_FLASH + 0x400000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_4M, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig
deleted file mode 100644
index 8dfc90cf8b..0000000000
--- a/board/sbc8641d/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SBC8641D
-
-config SYS_BOARD
-	default "sbc8641d"
-
-config SYS_CONFIG_NAME
-	default "sbc8641d"
-
-endif
diff --git a/board/sbc8641d/MAINTAINERS b/board/sbc8641d/MAINTAINERS
deleted file mode 100644
index a50b541ffe..0000000000
--- a/board/sbc8641d/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SBC8641D BOARD
-M:	Paul Gortmaker <paul.gortmaker@windriver.com>
-S:	Maintained
-F:	board/sbc8641d/
-F:	include/configs/sbc8641d.h
-F:	configs/sbc8641d_defconfig
diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile
deleted file mode 100644
index c48f82d3d9..0000000000
--- a/board/sbc8641d/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= sbc8641d.o
-obj-y	+= law.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8641d/README b/board/sbc8641d/README
deleted file mode 100644
index 4999b7763c..0000000000
--- a/board/sbc8641d/README
+++ /dev/null
@@ -1,49 +0,0 @@
-Wind River SBC8641D reference board
-===========================
-
-Created 06/14/2007 Joe Hamman
-Copyright 2007, Embedded Specialties, Inc.
-Copyright 2007 Wind River Systems, Inc.
------------------------------
-
-1. Building U-Boot
-------------------
-The SBC8641D code is known to build using ELDK 4.1.
-
-    $ make sbc8641d_config
-    Configuring for sbc8641d board...
-
-    $ make
-
-
-2. Switch and Jumper Settings
------------------------------
-All Jumpers & Switches are in their default positions.  Please refer to
-the board documentation for details.  Some settings control CPU voltages
-and settings may change with board revisions.
-
-3. Known limitations
---------------------
-PCI:
-	The PCI command may hang if no boards are present in either slot.
-
-4. Reflashing U-Boot
---------------------
-The board has two independent flash devices which can be used for dual
-booting, or for U-Boot backup and recovery.  A two pin jumper on the
-three pin JP10 determines which device is attached to /CS0 line.
-
-Assuming one device has a functional U-Boot, and the other device has
-a recently installed non-functional image, to perform a recovery from
-that non-functional image goes essentially as follows:
-
-a) power down the board and jumper JP10 to select the functional image.
-b) power on the board and let it get to U-Boot prompt.
-c) while on, using static precautions, move JP10 back to the failed image.
-d) use "md fff00000" to confirm you are looking at the failed image
-e) turn off write protect with "prot off all"
-f) get new image, i.e. "tftp 200000 /somepath/u-boot.bin"
-g) erase failed image: "erase FFF00000 FFF5FFFF"
-h) copy in new image: "cp.b 200000 FFF00000 60000"
-i) ensure new image is written: "md fff00000"
-k) power cycle the board and confirm new image works.
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
deleted file mode 100644
index b6c1847b14..0000000000
--- a/board/sbc8641d/ddr.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
deleted file mode 100644
index dc4696d123..0000000000
--- a/board/sbc8641d/law.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW (Local Access Window) configuration:
- *
- * 0x0000_0000	DDR			256M
- * 0x1000_0000	DDR2			256M
- * 0x8000_0000	PCIE1 MEM		512M
- * 0xa000_0000	PCIE2 MEM		512M
- * 0xc000_0000	RapidIO			512M
- * 0xe200_0000	PCIE1 IO		16M
- * 0xe300_0000	PCIE2 IO		16M
- * 0xf800_0000	CCSRBAR			2M
- * 0xfe00_0000	FLASH (boot bank)	32M
- *
- */
-
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
-#endif
-	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
deleted file mode 100644
index a67092daf4..0000000000
--- a/board/sbc8641d/sbc8641d.c
+++ /dev/null
@@ -1,268 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
- * Copyright 2007 Embedded Specialties, Inc.
- * Joe Hamman joe.hamman@embeddedspecialties.com
- *
- * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <pci.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-long int fixed_sdram (void);
-
-int board_early_init_f (void)
-{
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: Wind River SBC8641D\n");
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = fsl_ddr_sdram();
-#else
-	dram_size = fixed_sdram ();
-#endif
-
-	debug("    DDR: ");
-	gd->ram_size = dram_size;
-
-	return 0;
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram(void)
-{
-	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
-	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
-	uint *p;
-
-	puts ("SDRAM test phase 1:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	puts ("SDRAM test phase 2:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	puts ("SDRAM test passed.\n");
-	return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-long int fixed_sdram (void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
-	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
-	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
-	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
-	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
-	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
-	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
-	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
-
-	asm ("sync;isync");
-
-	udelay(500);
-
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
-	asm ("sync; isync");
-
-	udelay(500);
-	ddr = &immap->im_ddr2;
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
-	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
-	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
-	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
-	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
-	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
-	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
-	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
-	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
-	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
-	ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
-	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
-	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
-
-	asm ("sync;isync");
-
-	udelay(500);
-
-	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
-	asm ("sync; isync");
-
-	udelay(500);
-#endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif				/* !defined(CONFIG_SPD_EEPROM) */
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-	return 0;
-}
-#endif
-
-void sbc8641d_reset_board (void)
-{
-	puts ("Resetting board....\n");
-}
-
-/*
- * get_board_sys_clk
- *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long get_board_sys_clk (ulong dummy)
-{
-	int i;
-	ulong val = 0;
-
-	i = 5;
-	i &= 0x07;
-
-	switch (i) {
-	case 0:
-		val = 33000000;
-		break;
-	case 1:
-		val = 40000000;
-		break;
-	case 2:
-		val = 50000000;
-		break;
-	case 3:
-		val = 66000000;
-		break;
-	case 4:
-		val = 83000000;
-		break;
-	case 5:
-		val = 100000000;
-		break;
-	case 6:
-		val = 134000000;
-		break;
-	case 7:
-		val = 166000000;
-		break;
-	}
-
-	return val;
-}
-
-void board_reset(void)
-{
-#ifdef CONFIG_SYS_RESET_ADDRESS
-	ulong addr = CONFIG_SYS_RESET_ADDRESS;
-
-	/* flush and disable I/D cache */
-	__asm__ __volatile__ ("mfspr	3, 1008"	::: "r3");
-	__asm__ __volatile__ ("ori	5, 5, 0xcc00"	::: "r5");
-	__asm__ __volatile__ ("ori	4, 3, 0xc00"	::: "r4");
-	__asm__ __volatile__ ("andc	5, 3, 5"	::: "r5");
-	__asm__ __volatile__ ("sync");
-	__asm__ __volatile__ ("mtspr	1008, 4");
-	__asm__ __volatile__ ("isync");
-	__asm__ __volatile__ ("sync");
-	__asm__ __volatile__ ("mtspr	1008, 5");
-	__asm__ __volatile__ ("isync");
-	__asm__ __volatile__ ("sync");
-
-	/*
-	 * SRR0 has system reset vector, SRR1 has default MSR value
-	 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
-	 */
-	__asm__ __volatile__ ("mtspr	26, %0"		:: "r" (addr));
-	__asm__ __volatile__ ("li	4, (1 << 6)"	::: "r4");
-	__asm__ __volatile__ ("mtspr	27, 4");
-	__asm__ __volatile__ ("rfi");
-#endif
-}
diff --git a/board/spear/spear300/Kconfig b/board/spear/spear300/Kconfig
deleted file mode 100644
index 27360f32e4..0000000000
--- a/board/spear/spear300/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SPEAR300
-
-config SYS_BOARD
-	default "spear300"
-
-config SYS_VENDOR
-	default "spear"
-
-config SYS_SOC
-	default "spear"
-
-config SYS_CONFIG_NAME
-	default "spear3xx_evb"
-
-endif
diff --git a/board/spear/spear300/MAINTAINERS b/board/spear/spear300/MAINTAINERS
deleted file mode 100644
index 07152aefba..0000000000
--- a/board/spear/spear300/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-SPEAR300 BOARD
-M:	Vipin Kumar <vipin.kumar@st.com>
-S:	Maintained
-F:	board/spear/spear300/
-F:	include/configs/spear3xx_evb.h
-F:	configs/spear300_defconfig
-
-SPEAR300_NAND BOARD
-#M:	-
-S:	Maintained
-F:	configs/spear300_nand_defconfig
-F:	configs/spear300_usbtty_defconfig
-F:	configs/spear300_usbtty_nand_defconfig
diff --git a/board/spear/spear300/Makefile b/board/spear/spear300/Makefile
deleted file mode 100644
index d638bfc3ff..0000000000
--- a/board/spear/spear300/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= spear300.o
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
deleted file mode 100644
index a594538393..0000000000
--- a/board/spear/spear300/spear300.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <net.h>
-#include <netdev.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <linux/mtd/fsmc_nand.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	return spear_board_init(MACH_TYPE_SPEAR300);
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init()
-{
-	struct misc_regs *const misc_regs_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-#if defined(CONFIG_NAND_FSMC)
-	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG30) ||
-	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG31)) {
-
-		fsmc_nand_init(nand);
-	}
-#endif
-	return;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int ret = 0;
-
-#if defined(CONFIG_ETH_DESIGNWARE)
-	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
-		ret++;
-#endif
-	return ret;
-}
diff --git a/board/spear/spear310/Kconfig b/board/spear/spear310/Kconfig
deleted file mode 100644
index 0c95fa35a0..0000000000
--- a/board/spear/spear310/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SPEAR310
-
-config SYS_BOARD
-	default "spear310"
-
-config SYS_VENDOR
-	default "spear"
-
-config SYS_SOC
-	default "spear"
-
-config SYS_CONFIG_NAME
-	default "spear3xx_evb"
-
-endif
diff --git a/board/spear/spear310/MAINTAINERS b/board/spear/spear310/MAINTAINERS
deleted file mode 100644
index 4f9aa15b83..0000000000
--- a/board/spear/spear310/MAINTAINERS
+++ /dev/null
@@ -1,15 +0,0 @@
-SPEAR310 BOARD
-M:	Vipin Kumar <vipin.kumar@st.com>
-S:	Maintained
-F:	board/spear/spear310/
-F:	include/configs/spear3xx_evb.h
-F:	configs/spear310_defconfig
-
-SPEAR310_NAND BOARD
-#M:	-
-S:	Maintained
-F:	configs/spear310_nand_defconfig
-F:	configs/spear310_pnor_defconfig
-F:	configs/spear310_usbtty_defconfig
-F:	configs/spear310_usbtty_nand_defconfig
-F:	configs/spear310_usbtty_pnor_defconfig
diff --git a/board/spear/spear310/Makefile b/board/spear/spear310/Makefile
deleted file mode 100644
index 581d414324..0000000000
--- a/board/spear/spear310/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= spear310.o
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
deleted file mode 100644
index b4c3c0c5c7..0000000000
--- a/board/spear/spear310/spear310.c
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <net.h>
-#include <netdev.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <linux/mtd/fsmc_nand.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	return spear_board_init(MACH_TYPE_SPEAR310);
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init()
-{
-	struct misc_regs *const misc_regs_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-#if defined(CONFIG_NAND_FSMC)
-	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG30) ||
-	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG31)) {
-
-		fsmc_nand_init(nand);
-	}
-#endif
-	return;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int ret = 0;
-
-#if defined(CONFIG_ETH_DESIGNWARE)
-	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
-		ret++;
-#endif
-#if defined(CONFIG_MACB)
-	if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
-				CONFIG_MACB0_PHY) >= 0)
-		ret++;
-
-	if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE,
-				CONFIG_MACB1_PHY) >= 0)
-		ret++;
-
-	if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE,
-				CONFIG_MACB2_PHY) >= 0)
-		ret++;
-
-	if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE,
-				CONFIG_MACB3_PHY) >= 0)
-		ret++;
-#endif
-	return ret;
-}
diff --git a/board/spear/spear320/Kconfig b/board/spear/spear320/Kconfig
deleted file mode 100644
index df176230f4..0000000000
--- a/board/spear/spear320/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SPEAR320
-
-config SYS_BOARD
-	default "spear320"
-
-config SYS_VENDOR
-	default "spear"
-
-config SYS_SOC
-	default "spear"
-
-config SYS_CONFIG_NAME
-	default "spear3xx_evb"
-
-endif
diff --git a/board/spear/spear320/MAINTAINERS b/board/spear/spear320/MAINTAINERS
deleted file mode 100644
index bf7809230f..0000000000
--- a/board/spear/spear320/MAINTAINERS
+++ /dev/null
@@ -1,15 +0,0 @@
-SPEAR320 BOARD
-M:	Vipin Kumar <vipin.kumar@st.com>
-S:	Maintained
-F:	board/spear/spear320/
-F:	include/configs/spear3xx_evb.h
-F:	configs/spear320_defconfig
-
-SPEAR320_NAND BOARD
-#M:	-
-S:	Maintained
-F:	configs/spear320_nand_defconfig
-F:	configs/spear320_pnor_defconfig
-F:	configs/spear320_usbtty_defconfig
-F:	configs/spear320_usbtty_nand_defconfig
-F:	configs/spear320_usbtty_pnor_defconfig
diff --git a/board/spear/spear320/Makefile b/board/spear/spear320/Makefile
deleted file mode 100644
index 062cbc417a..0000000000
--- a/board/spear/spear320/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= spear320.o
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
deleted file mode 100644
index 291337b804..0000000000
--- a/board/spear/spear320/spear320.c
+++ /dev/null
@@ -1,78 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <net.h>
-#include <netdev.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <linux/mtd/fsmc_nand.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-
-#define PLGPIO_SEL_36	0xb3000028
-#define PLGPIO_IO_36	0xb3000038
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-static void spear_phy_reset(void)
-{
-	writel(0x10, PLGPIO_IO_36);
-	writel(0x10, PLGPIO_SEL_36);
-}
-
-int board_init(void)
-{
-	spear_phy_reset();
-	return spear_board_init(MACH_TYPE_SPEAR320);
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init()
-{
-	struct misc_regs *const misc_regs_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-#if defined(CONFIG_NAND_FSMC)
-	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG30) ||
-	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG31)) {
-
-		fsmc_nand_init(nand);
-	}
-#endif
-
-	return;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int ret = 0;
-
-#if defined(CONFIG_ETH_DESIGNWARE)
-	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
-		ret++;
-#endif
-#if defined(CONFIG_MACB)
-	if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
-				CONFIG_MACB0_PHY) >= 0)
-		ret++;
-#endif
-	return ret;
-}
diff --git a/board/spear/spear600/Kconfig b/board/spear/spear600/Kconfig
deleted file mode 100644
index d562e64f07..0000000000
--- a/board/spear/spear600/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SPEAR600
-
-config SYS_BOARD
-	default "spear600"
-
-config SYS_VENDOR
-	default "spear"
-
-config SYS_SOC
-	default "spear"
-
-config SYS_CONFIG_NAME
-	default "spear6xx_evb"
-
-endif
diff --git a/board/spear/spear600/MAINTAINERS b/board/spear/spear600/MAINTAINERS
deleted file mode 100644
index ddcd11a873..0000000000
--- a/board/spear/spear600/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-SPEAR600 BOARD
-M:	Vipin Kumar <vipin.kumar@st.com>
-S:	Maintained
-F:	board/spear/spear600/
-F:	include/configs/spear6xx_evb.h
-F:	configs/spear600_defconfig
-
-SPEAR600_NAND BOARD
-#M:	-
-S:	Maintained
-F:	configs/spear600_nand_defconfig
-F:	configs/spear600_usbtty_defconfig
-F:	configs/spear600_usbtty_nand_defconfig
diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile
deleted file mode 100644
index d25163e3f1..0000000000
--- a/board/spear/spear600/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= spear600.o
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
deleted file mode 100644
index 4706c52c12..0000000000
--- a/board/spear/spear600/spear600.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <net.h>
-#include <netdev.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <linux/mtd/fsmc_nand.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	return spear_board_init(MACH_TYPE_SPEAR600);
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init()
-{
-	struct misc_regs *const misc_regs_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-#if defined(CONFIG_NAND_FSMC)
-	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
-		fsmc_nand_init(nand);
-#endif
-	return;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int ret = 0;
-
-#if defined(CONFIG_ETH_DESIGNWARE)
-	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
-		ret++;
-#endif
-	return ret;
-}
diff --git a/board/spear/x600/Kconfig b/board/spear/x600/Kconfig
deleted file mode 100644
index 59f2b1ef56..0000000000
--- a/board/spear/x600/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-if TARGET_X600
-
-config SPL_LDSCRIPT
-	default "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
-
-config SYS_BOARD
-	default "x600"
-
-config SYS_VENDOR
-	default "spear"
-
-config SYS_SOC
-	default "spear"
-
-config SYS_CONFIG_NAME
-	default "x600"
-
-endif
diff --git a/board/spear/x600/MAINTAINERS b/board/spear/x600/MAINTAINERS
deleted file mode 100644
index bff6824945..0000000000
--- a/board/spear/x600/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-X600 BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/spear/x600/
-F:	include/configs/x600.h
-F:	configs/x600_defconfig
diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile
deleted file mode 100644
index 3ed8415777..0000000000
--- a/board/spear/x600/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-ifdef CONFIG_SPL_BUILD
-# necessary to create built-in.o
-obj- := __dummy__.o
-else
-obj-y	:= fpga.o x600.o
-endif
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
deleted file mode 100644
index 5140694b9e..0000000000
--- a/board/spear/x600/fpga.c
+++ /dev/null
@@ -1,265 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <log.h>
-#include <spartan3.h>
-#include <command.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_ssp.h>
-#include <linux/delay.h>
-
-/*
- * FPGA program pin configuration on X600:
- *
- * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
- * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
- * 16bit serial writes via this SSP port to write the data bits into the
- * FPGA.
- */
-#define CONFIG_SYS_FPGA_PROG		2
-#define CONFIG_SYS_FPGA_DONE		3
-
-/*
- * Set the active-low FPGA reset signal.
- */
-static void fpga_reset(int assert)
-{
-	/*
-	 * On x600 we have no means to toggle the FPGA reset signal
-	 */
-	debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
-}
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-static int fpga_pgm_fn(int assert, int flush, int cookie)
-{
-	debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
-
-	gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
-
-	return assert;
-}
-
-/*
- * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
- * asserted (low).
- */
-static int fpga_init_fn(int cookie)
-{
-	static int state;
-
-	debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
-
-	/*
-	 * On x600, the FPGA INIT signal is not connected to the SoC.
-	 * We can't read the INIT status. Let's return the "correct"
-	 * INIT signal state generated via a local state-machine.
-	 */
-	if (++state == 1) {
-		return 1;
-	} else {
-		state = 0;
-		return 0;
-	}
-}
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-static int fpga_done_fn(int cookie)
-{
-	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
-
-	/*
-	 * Wait for Tx-FIFO to become empty before looking for DONE
-	 */
-	while (!(readl(&ssp->sspsr) & SSPSR_TFE))
-		;
-
-	if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
-		return 1;
-	else
-		return 0;
-}
-
-/*
- * FPGA pre-configuration function. Just make sure that
- * FPGA reset is asserted to keep the FPGA from starting up after
- * configuration.
- */
-static int fpga_pre_config_fn(int cookie)
-{
-	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
-	fpga_reset(true);
-
-	return 0;
-}
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-static int fpga_post_config_fn(int cookie)
-{
-	int rc = 0;
-
-	debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
-
-	fpga_reset(true);
-	udelay(100);
-	fpga_reset(false);
-	udelay(100);
-
-	return rc;
-}
-
-static int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	/*
-	 * No dedicated clock signal on x600 (data & clock generated)
-	 * in SSP interface. So we don't have to do anything here.
-	 */
-	return assert_clk;
-}
-
-static int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
-	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
-	static int count;
-	static u16 data;
-
-	/*
-	 * First collect 16 bits of data
-	 */
-	data = data << 1;
-	if (assert_write)
-		data |= 1;
-
-	/*
-	 * If 16 bits are not available, return for more bits
-	 */
-	count++;
-	if (count != 16)
-		return assert_write;
-
-	count = 0;
-
-	/*
-	 * Wait for Tx-FIFO to become ready
-	 */
-	while (!(readl(&ssp->sspsr) & SSPSR_TNF))
-		;
-
-	/* Send 16 bits to FPGA via SSP bus */
-	writel(data, &ssp->sspdr);
-
-	return assert_write;
-}
-
-static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
-	fpga_pre_config_fn,
-	fpga_pgm_fn,
-	fpga_clk_fn,
-	fpga_init_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_post_config_fn,
-};
-
-static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-	XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
-};
-
-/*
- * Initialize the SelectMap interface.  We assume that the mode and the
- * initial state of all of the port pins have already been set!
- */
-static void fpga_serialslave_init(void)
-{
-	debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
-	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */
-}
-
-static int expi_setup(int freq)
-{
-	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
-
-	pll2_m = (freq * 2) / 1000;
-	pll2_n = 15;
-	pll2_p = 1;
-	expi_x = 1;
-	expi_y = 2;
-
-	/*
-	 * Disable reset, Low compression, Disable retiming, Enable Expi,
-	 * Enable soft reset, DMA, PLL2, Internal
-	 */
-	writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
-	       EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
-	       EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
-	       &misc->expi_clk_cfg);
-
-	/*
-	 * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
-	 * Enable PLL2, Disable reset
-	 */
-	writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
-	writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
-	       PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
-
-	/*
-	 * Disable soft reset
-	 */
-	clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
-
-	return 0;
-}
-
-/*
- * Initialize the fpga
- */
-int x600_init_fpga(void)
-{
-	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
-	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	/* Enable SSP2 clock */
-	writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
-	       &misc->periph1_clken);
-
-	/* Set EXPI clock to 45 MHz */
-	expi_setup(45000);
-
-	/* Configure GPIO directions */
-	gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
-	gpio_direction_input(CONFIG_SYS_FPGA_DONE);
-
-	writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
-	writel(SSPCR1_SSE, &ssp->sspcr1);
-
-	/*
-	 * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
-	 * speed.
-	 *
-	 * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
-	 * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
-	 */
-	writel(2, &ssp->sspcpsr);
-
-	fpga_init();
-	fpga_serialslave_init();
-
-	debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
-	fpga_add(fpga_xilinx, &fpga[0]);
-
-	return 0;
-}
diff --git a/board/spear/x600/fpga.h b/board/spear/x600/fpga.h
deleted file mode 100644
index f5e6f31a48..0000000000
--- a/board/spear/x600/fpga.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-int x600_init_fpga(void);
diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
deleted file mode 100644
index 9c30581ec0..0000000000
--- a/board/spear/x600/x600.c
+++ /dev/null
@@ -1,150 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <flash.h>
-#include <init.h>
-#include <micrel.h>
-#include <nand.h>
-#include <net.h>
-#include <netdev.h>
-#include <phy.h>
-#include <rtc.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-#include <linux/mtd/fsmc_nand.h>
-#include "fpga.h"
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	/*
-	 * X600 is equipped with an M41T82 RTC. This RTC has the
-	 * HT bit (Halt Update), which needs to be cleared upon
-	 * power-up. Otherwise the RTC is halted.
-	 */
-	rtc_reset();
-
-	return spear_board_init(MACH_TYPE_SPEAR600);
-}
-
-int board_late_init(void)
-{
-	/*
-	 * Monitor and env protection on by default
-	 */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
-		      CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
-		      2 * CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[0]);
-
-	/* Init FPGA subsystem */
-	x600_init_fpga();
-
-	return 0;
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init(void)
-{
-	struct misc_regs *const misc_regs_p =
-		(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
-		fsmc_nand_init(nand);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	unsigned short id1, id2;
-
-	/* check whether KSZ9031 or AR8035 has to be configured */
-	id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
-	id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
-
-	if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
-		/* PHY configuration for Micrel KSZ9031 */
-		printf("PHY KSZ9031 detected - ");
-
-		phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
-
-		/* control data pad skew - devaddr = 0x02, register = 0x04 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x0000);
-		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x0000);
-		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x0000);
-		/* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x03FF);
-	} else {
-		/* PHY configuration for Vitesse VSC8641 */
-		printf("PHY VSC8641 detected - ");
-
-		/* Extended PHY control 1, select GMII */
-		phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
-
-		/* Software reset necessary after GMII mode selction */
-		phy_reset(phydev);
-
-		/* Enable extended page register access */
-		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
-
-		/* 17e: Enhanced LED behavior, needs to be written twice */
-		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-
-		/* 16e: Enhanced LED method select */
-		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
-
-		/* Disable extended page register access */
-		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
-
-		/* Enable clock output pin */
-		phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
-	}
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int ret = 0;
-
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE,
-				  PHY_INTERFACE_MODE_GMII) >= 0)
-		ret++;
-
-	return ret;
-}
diff --git a/board/tqc/tqm834x/Kconfig b/board/tqc/tqm834x/Kconfig
deleted file mode 100644
index 028b8466e8..0000000000
--- a/board/tqc/tqm834x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_TQM834X
-
-config SYS_BOARD
-	default "tqm834x"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM834x"
-
-endif
diff --git a/board/tqc/tqm834x/MAINTAINERS b/board/tqc/tqm834x/MAINTAINERS
deleted file mode 100644
index 543ab1b552..0000000000
--- a/board/tqc/tqm834x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TQM834X BOARD
-#M:	-
-S:	Maintained
-F:	board/tqc/tqm834x/
-F:	include/configs/TQM834x.h
-F:	configs/TQM834x_defconfig
diff --git a/board/tqc/tqm834x/Makefile b/board/tqc/tqm834x/Makefile
deleted file mode 100644
index 3aafbf7928..0000000000
--- a/board/tqc/tqm834x/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright 2004 Freescale Semiconductor, Inc.
-
-obj-y += tqm834x.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c
deleted file mode 100644
index 92bda60765..0000000000
--- a/board/tqc/tqm834x/pci.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-/*
- * pci_init_board()
- *
- * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
- * per TQM834x design physical connections to external devices (PCI sockets)
- * are routed only to the PCI1 we do not account for the second one - this code
- * supports PCI1 module only. Should support for the PCI2 be required in the
- * future it needs a separate pci_controller structure (above) and handling -
- * please refer to other boards' implementation for dual PCI host controllers,
- * for example board/Marvell/db64360/pci.c, pci_init_board()
- *
- */
-void
-pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci1_regions };
-	u32 reg32;
-
-	/*
-	 * Configure PCI controller and PCI_CLK_OUTPUT
-	 *
-	 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
-	 * line actually used for clocking all external PCI devices in TQM83xx.
-	 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
-	 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
-	 * are known to hang the board; this issue is under investigation
-	 * (13 oct 05)
-	 */
-	reg32 = OCCR_PCICOE1;
-#if 0
-	/* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
-	reg32 = 0xff000000;
-#endif
-	if (clk->spmr & SPMR_CKID) {
-		/* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR
-		 * fields accordingly */
-		reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
-
-		reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
-			  | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
-			  | OCCR_PCICD6 | OCCR_PCICD7);
-	}
-
-	clk->occr = reg32;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
-
-	udelay(2000);
-
-	mpc83xx_pci_init(1, reg);
-}
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
deleted file mode 100644
index 17b4662c16..0000000000
--- a/board/tqc/tqm834x/tqm834x.c
+++ /dev/null
@@ -1,433 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <log.h>
-#include <mpc83xx.h>
-#include <asm/global_data.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/mmu.h>
-#include <pci.h>
-#include <flash.h>
-#include <linux/delay.h>
-#include <mtd/cfi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define IOSYNC			asm("eieio")
-#define ISYNC			asm("isync")
-#define SYNC			asm("sync")
-#define FPW			FLASH_PORT_WIDTH
-#define FPWV			FLASH_PORT_WIDTHV
-
-#define DDR_MAX_SIZE_PER_CS	0x20000000
-
-#if defined(DDR_CASLAT_20)
-#define TIMING_CASLAT		TIMING_CFG1_CASLAT_20
-#define MODE_CASLAT		DDR_MODE_CASLAT_20
-#else
-#define TIMING_CASLAT		TIMING_CFG1_CASLAT_25
-#define MODE_CASLAT		DDR_MODE_CASLAT_25
-#endif
-
-#define INITIAL_CS_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
-				CSCONFIG_COL_BIT_9)
-
-/* External definitions */
-ulong flash_get_size (ulong base, int banknum);
-
-/* Local functions */
-static int detect_num_flash_banks(void);
-static long int get_ddr_bank_size(short cs, long *base);
-static void set_cs_bounds(short cs, ulong base, ulong size);
-static void set_cs_config(short cs, long config);
-static void set_ddr_config(void);
-
-/* Local variable */
-static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-/**************************************************************************
- * Board initialzation after relocation to RAM. Used to detect the number
- * of Flash banks on TQM834x.
- */
-int board_early_init_r (void) {
-	/* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return 0;
-
-	/* detect the number of Flash banks */
-	return detect_num_flash_banks();
-}
-
-/**************************************************************************
- * DRAM initalization and size detection
- */
-int dram_init(void)
-{
-	long bank_size;
-	long size;
-	int cs;
-
-	/* during size detection, set up the max DDRLAW size */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE;
-	im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
-
-	/* set CS bounds to maximum size */
-	for(cs = 0; cs < 4; ++cs) {
-		set_cs_bounds(cs,
-			CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS),
-			DDR_MAX_SIZE_PER_CS);
-
-		set_cs_config(cs, INITIAL_CS_CONFIG);
-	}
-
-	/* configure ddr controller */
-	set_ddr_config();
-
-	udelay(200);
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
-		SDRAM_CFG_SREN |
-		SDRAM_CFG_SDRAM_TYPE_DDR1);
-	SYNC;
-
-	/* size detection */
-	debug("\n");
-	size = 0;
-	for(cs = 0; cs < 4; ++cs) {
-		debug("\nDetecting Bank%d\n", cs);
-
-		bank_size = get_ddr_bank_size(cs,
-			(long *)(CONFIG_SYS_SDRAM_BASE + size));
-		size += bank_size;
-
-		debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
-
-		/* exit if less than one bank */
-		if(size < DDR_MAX_SIZE_PER_CS) break;
-	}
-
-	gd->ram_size = size;
-
-	return 0;
-}
-
-/**************************************************************************
- * checkboard()
- */
-int checkboard (void)
-{
-	puts("Board: TQM834x\n");
-
-#ifdef CONFIG_PCI
-	volatile immap_t * immr;
-	u32 w, f;
-
-	immr = (immap_t *)CONFIG_SYS_IMMR;
-	if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
-		printf("PCI:   NOT in host mode..?!\n");
-		return 0;
-	}
-
-	/* get bus width */
-	w = 32;
-	if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
-		w = 64;
-
-	/* get clock */
-	f = gd->pci_clk;
-
-	printf("PCI1:  %d bit, %d MHz\n", w, f / 1000000);
-#else
-	printf("PCI:   disabled\n");
-#endif
-	return 0;
-}
-
-
-/**************************************************************************
- *
- * Local functions
- *
- *************************************************************************/
-
-/**************************************************************************
- * Detect the number of flash banks (1 or 2). Store it in
- * a global variable tqm834x_num_flash_banks.
- * Bank detection code based on the Monitor code.
- */
-static int detect_num_flash_banks(void)
-{
-	typedef unsigned long FLASH_PORT_WIDTH;
-	typedef volatile unsigned long FLASH_PORT_WIDTHV;
-	FPWV *bank1_base;
-	FPWV *bank2_base;
-	FPW bank1_read;
-	FPW bank2_read;
-	ulong bank1_size;
-	ulong bank2_size;
-	ulong total_size;
-
-	cfi_flash_num_flash_banks = 2;	/* assume two banks */
-
-	/* Get bank 1 and 2 information */
-	bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0);
-	debug("Bank1 size: %lu\n", bank1_size);
-	bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1);
-	debug("Bank2 size: %lu\n", bank2_size);
-	total_size = bank1_size + bank2_size;
-
-	if (bank2_size > 0) {
-		/* Seems like we've got bank 2, but maybe it's mirrored 1 */
-
-		/* Set the base addresses */
-		bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
-		bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size);
-
-		/* Put bank 2 into CFI command mode and read */
-		bank2_base[0x55] = 0x00980098;
-		IOSYNC;
-		ISYNC;
-		bank2_read = bank2_base[0x10];
-
-		/* Read from bank 1 (it's in read mode) */
-		bank1_read = bank1_base[0x10];
-
-		/* Reset Flash */
-		bank1_base[0] = 0x00F000F0;
-		bank2_base[0] = 0x00F000F0;
-
-		if (bank2_read == bank1_read) {
-			/*
-			 * Looks like just one bank, but not sure yet. Let's
-			 * read from bank 2 in autosoelect mode.
-			 */
-			bank2_base[0x0555] = 0x00AA00AA;
-			bank2_base[0x02AA] = 0x00550055;
-			bank2_base[0x0555] = 0x00900090;
-			IOSYNC;
-			ISYNC;
-			bank2_read = bank2_base[0x10];
-
-			/* Read from bank 1 (it's in read mode) */
-			bank1_read = bank1_base[0x10];
-
-			/* Reset Flash */
-			bank1_base[0] = 0x00F000F0;
-			bank2_base[0] = 0x00F000F0;
-
-			if (bank2_read == bank1_read) {
-				/*
-				 * In both CFI command and autoselect modes,
-				 * we got the some data reading from Flash.
-				 * There is only one mirrored bank.
-				 */
-				cfi_flash_num_flash_banks = 1;
-				total_size = bank1_size;
-			}
-		}
-	}
-
-	debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
-
-	/* set OR0 and BR0 */
-	set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 |
-		   OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM));
-	set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
-		   (BR_MS_GPCM | BR_PS_32 | BR_V));
-
-	return (0);
-}
-
-/*************************************************************************
- * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
- */
-static long int get_ddr_bank_size(short cs, long *base)
-{
-	/* This array lists all valid DDR SDRAM configurations, with
-	 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
-	 * The last entry has to to have size equal 0 and is igonred during
-	 * autodection. Bank sizes must be in increasing order of size
-	 */
-	struct {
-		long row;
-		long col;
-		long size;
-	} conf[] = {
-		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_8,	32 << 20},
-		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_9,	64 << 20},
-		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_10,	128 << 20},
-		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_9,	128 << 20},
-		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_10,	256 << 20},
-		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_11,	512 << 20},
-		{CSCONFIG_ROW_BIT_14,	CSCONFIG_COL_BIT_10,	512 << 20},
-		{CSCONFIG_ROW_BIT_14,	CSCONFIG_COL_BIT_11,	1024 << 20},
-		{0,			0,			0}
-	};
-
-	int i;
-	int detected;
-	long size;
-
-	detected = -1;
-	for(i = 0; conf[i].size != 0; ++i) {
-
-		/* set sdram bank configuration */
-		set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
-
-		debug("Getting RAM size...\n");
-		size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
-
-		if((size == conf[i].size) && (i == detected + 1))
-			detected = i;
-
-		debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
-			conf[i].row,
-			conf[i].col,
-			conf[i].size >> 20,
-			base,
-			size >> 20);
-	}
-
-	if(detected == -1){
-		/* disable empty cs */
-		debug("\nNo valid configurations for CS%d, disabling...\n", cs);
-		set_cs_config(cs, 0);
-		return 0;
-	}
-
-	debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
-			conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
-
-	/* configure cs ro detected params */
-	set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
-			conf[detected].col);
-
-	set_cs_bounds(cs, (long)base, conf[detected].size);
-
-	return(conf[detected].size);
-}
-
-/**************************************************************************
- * Sets DDR bank CS bounds.
- */
-static void set_cs_bounds(short cs, ulong base, ulong size)
-{
-	debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);
-	if(size == 0){
-		im->ddr.csbnds[cs].csbnds = 0x00000000;
-	} else {
-		im->ddr.csbnds[cs].csbnds =
-			((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-			(((base + size - 1) >> CSBNDS_EA_SHIFT) &
-				CSBNDS_EA);
-	}
-	SYNC;
-}
-
-/**************************************************************************
- * Sets DDR banks CS configuration.
- * config == 0x00000000 disables the CS.
- */
-static void set_cs_config(short cs, long config)
-{
-	debug("Setting config %08lx for cs %d\n", config, cs);
-	im->ddr.cs_config[cs] = config;
-	SYNC;
-}
-
-/**************************************************************************
- * Sets DDR clocks, timings and configuration.
- */
-static void set_ddr_config(void) {
-	/* clock control */
-	im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
-		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
-	SYNC;
-
-	/* timing configuration */
-	im->ddr.timing_cfg_1 =
-		(4 << TIMING_CFG1_PRETOACT_SHIFT) |
-		(7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
-		(4 << TIMING_CFG1_ACTTORW_SHIFT)  |
-		(5 << TIMING_CFG1_REFREC_SHIFT)   |
-		(3 << TIMING_CFG1_WRREC_SHIFT)    |
-		(3 << TIMING_CFG1_ACTTOACT_SHIFT) |
-		(1 << TIMING_CFG1_WRTORD_SHIFT)   |
-		(TIMING_CFG1_CASLAT & TIMING_CASLAT);
-
-	im->ddr.timing_cfg_2 =
-		TIMING_CFG2_CPO_DEF |
-		(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
-	SYNC;
-
-	/* don't enable DDR controller yet */
-	im->ddr.sdram_cfg =
-		SDRAM_CFG_SREN |
-		SDRAM_CFG_SDRAM_TYPE_DDR1;
-	SYNC;
-
-	/* Set SDRAM mode */
-	im->ddr.sdram_mode =
-		((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
-			SDRAM_MODE_ESD_SHIFT) |
-		((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
-			SDRAM_MODE_SD_SHIFT) |
-		((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
-			MODE_CASLAT);
-	SYNC;
-
-	/* Set fast SDRAM refresh rate */
-	im->ddr.sdram_interval =
-		(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
-		(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
-	SYNC;
-
-	/* Workaround for DDR6 Erratum
-	 * see MPC8349E Device Errata Rev.8, 2/2006
-	 * This workaround influences the MPC internal "input enables"
-	 * dependent on CAS latency and MPC revision. According to errata
-	 * sheet the internal reserved registers for this workaround are
-	 * not available from revision 2.0 and up.
-	 */
-
-	/* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
-	 * (0x200)
-	 */
-	if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
-
-		/* There is a internal reserved register at IMMRBAR+0x2F00
-		 * which has to be written with a certain value defined by
-		 * errata sheet.
-		 */
-		u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
-
-#if defined(DDR_CASLAT_20)
-		*reserved_p = 0x201c0000;
-#else
-		*reserved_p = 0x202c0000;
-#endif
-	}
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif	/* CONFIG_PCI */
-
-	return 0;
-}
-#endif	/* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ve8313/Kconfig b/board/ve8313/Kconfig
deleted file mode 100644
index a63744b154..0000000000
--- a/board/ve8313/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_VE8313
-
-config SYS_BOARD
-	default "ve8313"
-
-config SYS_CONFIG_NAME
-	default "ve8313"
-
-endif
diff --git a/board/ve8313/MAINTAINERS b/board/ve8313/MAINTAINERS
deleted file mode 100644
index e3ca3325fc..0000000000
--- a/board/ve8313/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VE8313 BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	board/ve8313/
-F:	include/configs/ve8313.h
-F:	configs/ve8313_defconfig
diff --git a/board/ve8313/Makefile b/board/ve8313/Makefile
deleted file mode 100644
index d656bd93ab..0000000000
--- a/board/ve8313/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= ve8313.o
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
deleted file mode 100644
index 78d401e955..0000000000
--- a/board/ve8313/ve8313.c
+++ /dev/null
@@ -1,209 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Author: Scott Wood <scottwood@freescale.com>
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <ns16550.h>
-#include <nand.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void disable_addr_trans (void);
-extern void enable_addr_trans (void);
-
-int checkboard(void)
-{
-	puts("Board: ve8313\n");
-	return 0;
-}
-
-static long fixed_sdram(void)
-{
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize_log2 = __ilog2(msize);
-
-	out_be32(&im->sysconf.ddrlaw[0].bar,
-		(CONFIG_SYS_SDRAM_BASE & 0xfffff000));
-	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
-	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
-
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	__udelay(50000);
-
-#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	out_be32(&im->ddr.csbnds[0].csbnds,
-		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
-			CSBNDS_EA));
-	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
-
-	/* Currently we use only one CS, so disable the other bank. */
-	out_be32(&im->ddr.cs_config[1], 0);
-
-	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
-	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
-	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
-	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
-	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-
-	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
-
-	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
-	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
-	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
-
-	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
-	sync();
-
-	/* enable DDR controller */
-	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
-
-	/* now check the real size */
-	disable_addr_trans ();
-	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
-	enable_addr_trans ();
-#endif
-
-	return msize;
-}
-
-int dram_init(void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &im->im_lbc;
-	u32 msize;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	msize = fixed_sdram();
-
-	/* Local Bus setup lbcr and mrtpr */
-	out_be32(&lbc->lbcr, 0x00040000);
-	out_be32(&lbc->mrtpr, 0x20000000);
-	sync();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	gd->ram_size = msize;
-
-	return 0;
-}
-
-#define VE8313_WDT_EN	0x00020000
-#define VE8313_WDT_TRIG	0x00040000
-
-int board_early_init_f (void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
-
-#if defined(CONFIG_HW_WATCHDOG)
-	/* enable WDT */
-	clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
-#else
-	/* disable WDT */
-	setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
-#endif
-	/* set WDT pins as output */
-	setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
-
-	return 0;
-}
-
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
-	unsigned long reg;
-
-	reg = in_be32(&gpio->dat);
-	if (reg & VE8313_WDT_TRIG)
-		clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
-	else
-		setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
-}
-#endif
-
-
-#if defined(CONFIG_PCI)
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci_regions };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	setbits_be32(&clk->occr, 0xe0000000);
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
-	out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
-	out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
-
-	mpc83xx_pci_init(1, reg);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index b5c6900021..4932030547 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -4,7 +4,6 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
-obj-$(CONFIG_ARCH_MPC8572)		+= fsl_8xxx_clk.o
 obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
 obj-$(CONFIG_ARCH_P2020)		+= fsl_8xxx_clk.o
 obj-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
diff --git a/board/xes/xpedite517x/Kconfig b/board/xes/xpedite517x/Kconfig
deleted file mode 100644
index 91bbd22451..0000000000
--- a/board/xes/xpedite517x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE517X
-
-config SYS_BOARD
-	default "xpedite517x"
-
-config SYS_VENDOR
-	default "xes"
-
-config SYS_CONFIG_NAME
-	default "xpedite517x"
-
-endif
diff --git a/board/xes/xpedite517x/MAINTAINERS b/board/xes/xpedite517x/MAINTAINERS
deleted file mode 100644
index 26e0acccb0..0000000000
--- a/board/xes/xpedite517x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE517X BOARD
-M:	Peter Tyser <ptyser@xes-inc.com>
-S:	Maintained
-F:	board/xes/xpedite517x/
-F:	include/configs/xpedite517x.h
-F:	configs/xpedite517x_defconfig
diff --git a/board/xes/xpedite517x/Makefile b/board/xes/xpedite517x/Makefile
deleted file mode 100644
index 10ac76a37a..0000000000
--- a/board/xes/xpedite517x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= xpedite517x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
deleted file mode 100644
index a3fd2fc8ca..0000000000
--- a/board/xes/xpedite517x/ddr.c
+++ /dev/null
@@ -1,124 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <log.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
-{
-	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
-		sizeof(ddr2_spd_eeprom_t));
-}
-
-/*
- * There are four board-specific SDRAM timing parameters which must be
- * calculated based on the particular PCB artwork.  These are:
- *   1.) CPO (Read Capture Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths and
- *                   chip-specific internal delays.
- *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths.
- *                   Unless clock and DQ lanes are very different
- *                   lengths (>2"), this should be set to the nominal value
- *                   of 1/2 clock delay.
- *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *           - DDR_SDRAM_CLK_CNTL register
- *           Source: Signal Integrity Simulations
- *   4.) 2T Timing on Addr/Ctl
- *           - TIMING_CFG_2 register
- *           Source: Signal Integrity Simulations
- *           Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- *     PCB routing on the XPedite5170 is nearly identical to the XPedite5370
- *     so we use the XPedite5370 settings as a basis for the XPedite5170.
- */
-
-typedef struct board_memctl_options {
-	uint16_t datarate_mhz_low;
-	uint16_t datarate_mhz_high;
-	uint8_t clk_adjust;
-	uint8_t cpo_override;
-	uint8_t write_data_delay;
-} board_memctl_options_t;
-
-static struct board_memctl_options bopts_ctrl[][2] = {
-	{
-		/* Controller 0 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 9,
-			.write_data_delay	= 2,
-		},
-	},
-	{
-		/* Controller 1 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 7,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-	},
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-			dimm_params_t *pdimm,
-			unsigned int ctrl_num)
-{
-	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
-	sys_info_t sysinfo;
-	int i;
-	unsigned int datarate;
-
-	get_sys_info(&sysinfo);
-	datarate = get_ddr_freq(0) / 1000000;
-
-	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
-		if ((bopts[i].datarate_mhz_low <= datarate) &&
-		    (bopts[i].datarate_mhz_high >= datarate)) {
-			debug("controller %d:\n", ctrl_num);
-			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
-			debug(" cpo = %d\n", bopts[i].cpo_override);
-			debug(" write_data_delay = %d\n",
-				bopts[i].write_data_delay);
-			popts->clk_adjust = bopts[i].clk_adjust;
-			popts->cpo_override = bopts[i].cpo_override;
-			popts->write_data_delay = bopts[i].write_data_delay;
-		}
-	}
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/xes/xpedite517x/law.c b/board/xes/xpedite517x/law.c
deleted file mode 100644
index b82f9f0d3b..0000000000
--- a/board/xes/xpedite517x/law.c
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE
-	/* NAND LAW covers 2 NAND flashes */
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
deleted file mode 100644
index 8a5b52c495..0000000000
--- a/board/xes/xpedite517x/xpedite517x.c
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-#include "../common/fsl_8xxx_misc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-#endif
-
-/*
- * Print out which flash was booted from and if booting from the 2nd flash,
- * swap flash chip selects to maintain consistent flash numbering/addresses.
- */
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	phys_size_t dram_size = fsl_ddr_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/* Initialize and enable DDR ECC */
-	ddr_enable_ecc(dram_size);
-#endif
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/xes/xpedite520x/Kconfig b/board/xes/xpedite520x/Kconfig
deleted file mode 100644
index 9c0c2461fd..0000000000
--- a/board/xes/xpedite520x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE520X
-
-config SYS_BOARD
-	default "xpedite520x"
-
-config SYS_VENDOR
-	default "xes"
-
-config SYS_CONFIG_NAME
-	default "xpedite520x"
-
-endif
diff --git a/board/xes/xpedite520x/MAINTAINERS b/board/xes/xpedite520x/MAINTAINERS
deleted file mode 100644
index f7bd437cc6..0000000000
--- a/board/xes/xpedite520x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE520X BOARD
-M:	Peter Tyser <ptyser@xes-inc.com>
-S:	Maintained
-F:	board/xes/xpedite520x/
-F:	include/configs/xpedite520x.h
-F:	configs/xpedite520x_defconfig
diff --git a/board/xes/xpedite520x/Makefile b/board/xes/xpedite520x/Makefile
deleted file mode 100644
index 12e75da5b3..0000000000
--- a/board/xes/xpedite520x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Extreme Engineering Solutions, Inc.
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= xpedite520x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
deleted file mode 100644
index c142bec406..0000000000
--- a/board/xes/xpedite520x/ddr.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
-{
-	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
-
-	/* We use soldered memory, but use an SPD EEPROM to describe it.
-	 * The SPD has an unspecified dimm type, but the DDR2 initialization
-	 * code requires a specific type to be specified. This sets the type
-	 * as a standard unregistered SO-DIMM. */
-	if (spd->dimm_type == 0) {
-		spd->dimm_type = 0x4;
-		((uchar *)spd)[63] += 0x4;
-	}
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 9;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
deleted file mode 100644
index 10613ead3f..0000000000
--- a/board/xes/xpedite520x/law.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite520x/tlb.c b/board/xes/xpedite520x/tlb.c
deleted file mode 100644
index d45f532861..0000000000
--- a/board/xes/xpedite520x/tlb.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* W**G* - NOR flashes */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* *I*G* - NAND flash */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 2, BOOKE_PAGESZ_1M, 1),
-
-#if CONFIG_PCI1
-	/* *I*G* - PCI MEM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 3, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#if CONFIG_PCI2
-	/* *I*G* - PCI MEM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 4, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
-	/* *I*G* - PCI IO */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 5, BOOKE_PAGESZ_16M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite520x/xpedite520x.c b/board/xes/xpedite520x/xpedite520x.c
deleted file mode 100644
index 63e1e0efe5..0000000000
--- a/board/xes/xpedite520x/xpedite520x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2004, 2007 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-
-	/*
-	 * Remap NOR flash region to caching-inhibited
-	 * so that flash can be erased/programmed properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* Invalidate existing TLB entry for NOR flash */
-	disable_tlb(0);
-	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/xes/xpedite537x/Kconfig b/board/xes/xpedite537x/Kconfig
deleted file mode 100644
index 35b3917a6d..0000000000
--- a/board/xes/xpedite537x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE537X
-
-config SYS_BOARD
-	default "xpedite537x"
-
-config SYS_VENDOR
-	default "xes"
-
-config SYS_CONFIG_NAME
-	default "xpedite537x"
-
-endif
diff --git a/board/xes/xpedite537x/MAINTAINERS b/board/xes/xpedite537x/MAINTAINERS
deleted file mode 100644
index b6123acc0f..0000000000
--- a/board/xes/xpedite537x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE537X BOARD
-M:	Peter Tyser <ptyser@xes-inc.com>
-S:	Maintained
-F:	board/xes/xpedite537x/
-F:	include/configs/xpedite537x.h
-F:	configs/xpedite537x_defconfig
diff --git a/board/xes/xpedite537x/Makefile b/board/xes/xpedite537x/Makefile
deleted file mode 100644
index 82575cf05e..0000000000
--- a/board/xes/xpedite537x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Extreme Engineering Solutions, Inc.
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= xpedite537x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
deleted file mode 100644
index f55102a072..0000000000
--- a/board/xes/xpedite537x/ddr.c
+++ /dev/null
@@ -1,234 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <log.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
-{
-	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
-		 sizeof(ddr2_spd_eeprom_t));
-}
-
-/*
- * There are four board-specific SDRAM timing parameters which must be
- * calculated based on the particular PCB artwork.  These are:
- *   1.) CPO (Read Capture Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths and
- *                   chip-specific internal delays.
- *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths.
- *                   Unless clock and DQ lanes are very different
- *                   lengths (>2"), this should be set to the nominal value
- *                   of 1/2 clock delay.
- *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *           - DDR_SDRAM_CLK_CNTL register
- *           Source: Signal Integrity Simulations
- *   4.) 2T Timing on Addr/Ctl
- *           - TIMING_CFG_2 register
- *           Source: Signal Integrity Simulations
- *           Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- *     ====== XPedite5370 DDR2-600 read delay calculations ======
- *
- *     See Freescale's App Note AN2583 as refrence.  This document also
- *     contains the chip-specific delays for 8548E, 8572, etc.
- *
- *     For MPC8572E
- *     Minimum chip delay (Ch 0): 1.372ns
- *     Maximum chip delay (Ch 0): 2.914ns
- *     Minimum chip delay (Ch 1): 1.220ns
- *     Maximum chip delay (Ch 1): 2.595ns
- *
- *     CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
- *
- *     Minimum delay calc (Ch 0):
- *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- *     2.3" * 180 - 400ps     + 1.9" * 180         + 2080ps     + 1372ps
- *                                                 = 3808ps
- *                                                 = 3.808ns
- *
- *     Maximum delay calc (Ch 0):
- *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
- *     2.3" * 180 + 400ps     + 2.4" * 180         + 2080ps     + 2914ps
- *                                                 = 6240ps
- *                                                 = 6.240ns
- *
- *     Minimum delay calc (Ch 1):
- *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- *     1.46" * 180- 400ps     + 0.7" * 180         + 2080ps     + 1220ps
- *                                                 = 3288ps
- *                                                 = 3.288ns
- *
- *     Maximum delay calc (Ch 1):
- *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
- *     1.46" * 180+ 400ps     + 1.1" * 180         + 2080ps     + 2595ps
- *                                                 = 5536ps
- *                                                 = 5.536ns
- *
- *     Ch.0: 3.808ns to 6.240ns additional delay needed  (pick 5ns as target)
- *              This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
- *     Ch.1: 3.288ns to 5.536ns additional delay needed  (pick 4.4ns as target)
- *              This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
- *
- *
- *     ====== XPedite5370 DDR2-800 read delay calculations ======
- *
- *     See Freescale's App Note AN2583 as refrence.  This document also
- *     contains the chip-specific delays for 8548E, 8572, etc.
- *
- *     For MPC8572E
- *     Minimum chip delay (Ch 0): 1.372ns
- *     Maximum chip delay (Ch 0): 2.914ns
- *     Minimum chip delay (Ch 1): 1.220ns
- *     Maximum chip delay (Ch 1): 2.595ns
- *
- *     CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
- *
- *     Minimum delay calc (Ch 0):
- *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- *     2.3" * 180 - 350ps     + 1.9" * 180         + 1563ps     + 1372ps
- *                                                 = 3341ps
- *                                                 = 3.341ns
- *
- *     Maximum delay calc (Ch 0):
- *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
- *     2.3" * 180 + 350ps     + 2.4" * 180         + 1563ps     + 2914ps
- *                                                 = 5673ps
- *                                                 = 5.673ns
- *
- *     Minimum delay calc (Ch 1):
- *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- *     1.46" * 180- 350ps     + 0.7" * 180         + 1563ps     + 1220ps
- *                                                 = 2822ps
- *                                                 = 2.822ns
- *
- *     Maximum delay calc (Ch 1):
- *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
- *     1.46" * 180+ 350ps     + 1.1" * 180         + 1563ps     + 2595ps
- *                                                 = 4968ps
- *                                                 = 4.968ns
- *
- *     Ch.0: 3.341ns to 5.673ns additional delay needed  (pick 4.5ns as target)
- *              This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
- *     Ch.1: 2.822ns to 4.968ns additional delay needed  (pick 3.9ns as target)
- *              This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
- *
- * Write latency (WR_DATA_DELAY) is calculated by doing the following:
- *
- *      The DDR SDRAM specification requires DQS be received no sooner than
- *      75% of an SDRAM clock periodÂ—and no later than 125% of a clock
- *      periodÂ—from the capturing clock edge of the command/address at the
- *      SDRAM.
- *
- * Based on the above tracelengths, the following are calculated:
- *      Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 =  0.342ns
- *      Ch. 0 8572 to DRAM propagation (CLKs) :     2.3" * 180 =  0.414ns
- *      Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 =  0.126ns
- *      Ch. 1 8572 to DRAM propagation (CLKs   ) : 1.47" * 180 =  0.264ns
- *
- * Difference in arrival time CLK vs. DQS:
- *      Ch. 0 0.072ns
- *      Ch. 1 0.138ns
- *
- *      Both of these values are much less than 25% of the clock
- *      period at DDR2-600 or DDR2-800, so no additional delay is needed over
- *      the 1/2 cycle which normally aligns the first DQS transition
- *      exactly WL (CAS latency minus one cycle) after the CAS strobe.
- *      See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
- *      terminology corresponds to exactly one clock period delay after
- *      the CAS strobe. (due to the fact that the "delay" is referenced
- *      from the *falling* edge of the CLK, just after the rising edge
- *      which the CAS strobe is latched on.
- */
-
-typedef struct board_memctl_options {
-	uint16_t datarate_mhz_low;
-	uint16_t datarate_mhz_high;
-	uint8_t clk_adjust;
-	uint8_t cpo_override;
-	uint8_t write_data_delay;
-} board_memctl_options_t;
-
-static struct board_memctl_options bopts_ctrl[][2] = {
-	{
-		/* Controller 0 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 9,
-			.write_data_delay	= 2,
-		},
-	},
-	{
-		/* Controller 1 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 7,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-	},
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-			   dimm_params_t *pdimm,
-			   unsigned int ctrl_num)
-{
-	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
-	sys_info_t sysinfo;
-	int i;
-	unsigned int datarate;
-
-	get_sys_info(&sysinfo);
-	datarate = sysinfo.freq_ddrbus / 1000 / 1000;
-
-	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
-		if ((bopts[i].datarate_mhz_low <= datarate) &&
-		    (bopts[i].datarate_mhz_high >= datarate)) {
-			debug("controller %d:\n", ctrl_num);
-			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
-			debug(" cpo = %d\n", bopts[i].cpo_override);
-			debug(" write_data_delay = %d\n",
-			      bopts[i].write_data_delay);
-			popts->clk_adjust = bopts[i].clk_adjust;
-			popts->cpo_override = bopts[i].cpo_override;
-			popts->write_data_delay = bopts[i].write_data_delay;
-		}
-	}
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/xes/xpedite537x/law.c b/board/xes/xpedite537x/law.c
deleted file mode 100644
index a1f375900c..0000000000
--- a/board/xes/xpedite537x/law.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite537x/tlb.c b/board/xes/xpedite537x/tlb.c
deleted file mode 100644
index 6d50360f06..0000000000
--- a/board/xes/xpedite537x/tlb.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* W**G* - NOR flashes */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* *I*G* - NAND flash */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 2, BOOKE_PAGESZ_1M, 1),
-
-	/* **M** - Boot page for secondary processors */
-	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		0, 3, BOOKE_PAGESZ_4K, 1),
-
-#ifdef CONFIG_PCIE1
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 4, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_PCIE2
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_PCIE3
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 6, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 7, BOOKE_PAGESZ_64M, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c
deleted file mode 100644
index 437b57d4ff..0000000000
--- a/board/xes/xpedite537x/xpedite537x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
-	/*
-	 * Remap NOR flash region to caching-inhibited
-	 * so that flash can be erased/programmed properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* Invalidate existing TLB entry for NOR flash */
-	disable_tlb(0);
-	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/xes/xpedite550x/Kconfig b/board/xes/xpedite550x/Kconfig
deleted file mode 100644
index 1b00137a48..0000000000
--- a/board/xes/xpedite550x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE550X
-
-config SYS_BOARD
-	default "xpedite550x"
-
-config SYS_VENDOR
-	default "xes"
-
-config SYS_CONFIG_NAME
-	default "xpedite550x"
-
-endif
diff --git a/board/xes/xpedite550x/MAINTAINERS b/board/xes/xpedite550x/MAINTAINERS
deleted file mode 100644
index 017f368757..0000000000
--- a/board/xes/xpedite550x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE550X BOARD
-M:	Peter Tyser <ptyser@xes-inc.com>
-S:	Maintained
-F:	board/xes/xpedite550x/
-F:	include/configs/xpedite550x.h
-F:	configs/xpedite550x_defconfig
diff --git a/board/xes/xpedite550x/Makefile b/board/xes/xpedite550x/Makefile
deleted file mode 100644
index 1aacb375cc..0000000000
--- a/board/xes/xpedite550x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007-2008 Freescale Semiconductor, Inc.
-
-obj-y	+= xpedite550x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
deleted file mode 100644
index ad52c9455b..0000000000
--- a/board/xes/xpedite550x/ddr.c
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
-{
-	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
-		 sizeof(ddr3_spd_eeprom_t));
-}
-
-/*
- *     There are traditionally three board-specific SDRAM timing parameters
- *     which must be calculated based on the particular PCB artwork.  These are:
- *     1.) CPO (Read Capture Delay)
- *	       - TIMING_CFG_2 register
- *	       Source: Calculation based on board trace lengths and
- *		       chip-specific internal delays.
- *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *	       - DDR_SDRAM_CLK_CNTL register
- *	       Source: Signal Integrity Simulations
- *     3.) 2T Timing on Addr/Ctl
- *	       - TIMING_CFG_2 register
- *	       Source: Signal Integrity Simulations
- *	       Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- *     ====== XPedite550x DDR3-800 read delay calculations ======
- *
- *     The P2020 processor provides an autoleveling option. Setting CPO to
- *     0x1f enables this auto configuration.
- */
-
-typedef struct {
-	unsigned short datarate_mhz_low;
-	unsigned short datarate_mhz_high;
-	unsigned char clk_adjust;
-	unsigned char cpo;
-} board_specific_parameters_t;
-
-const board_specific_parameters_t board_specific_parameters[][20] = {
-	{
-		/* Controller 0 */
-		{
-			/* DDR3-600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo			= 31,
-		},
-		{
-			/* DDR3-800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo			= 31,
-		},
-	},
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const board_specific_parameters_t *pbsp =
-				&(board_specific_parameters[ctrl_num][0]);
-	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
-				sizeof(board_specific_parameters[0][0]);
-	u32 i;
-	ulong ddr_freq;
-
-	/*
-	 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
-	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
-	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
-	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
-	 */
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i&1) {	/* odd CS */
-			popts->cs_local_opts[i].odt_rd_cfg = 0;
-			popts->cs_local_opts[i].odt_wr_cfg = 0;
-		} else {	/* even CS */
-			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
-				popts->cs_local_opts[i].odt_rd_cfg = 0;
-				popts->cs_local_opts[i].odt_wr_cfg = 4;
-			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
-				popts->cs_local_opts[i].odt_rd_cfg = 3;
-				popts->cs_local_opts[i].odt_wr_cfg = 3;
-			}
-		}
-	}
-
-	/*
-	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-
-	for (i = 0; i < num_params; i++) {
-		if (ddr_freq >= pbsp->datarate_mhz_low &&
-		    ddr_freq <= pbsp->datarate_mhz_high) {
-			popts->clk_adjust = pbsp->clk_adjust;
-			popts->cpo_override = pbsp->cpo;
-			popts->twot_en = 0;
-			break;
-		}
-		pbsp++;
-	}
-
-	if (i == num_params) {
-		printf("Warning: board specific timing not found "
-		"for data rate %lu MT/s!\n", ddr_freq);
-	}
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-
-	/*
-	 * Enable on-die termination.
-	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
-	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
-	 * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
-	 */
-	popts->rtt_override = 1;
-	popts->rtt_override_value = 3;
-}
diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c
deleted file mode 100644
index 1e2d604d9d..0000000000
--- a/board/xes/xpedite550x/law.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite550x/tlb.c b/board/xes/xpedite550x/tlb.c
deleted file mode 100644
index 7cb6cd6770..0000000000
--- a/board/xes/xpedite550x/tlb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* W**G* - NOR flashes */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* *I*G* - NAND flash */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 2, BOOKE_PAGESZ_1M, 1),
-
-	/* **M** - Boot page for secondary processors */
-	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		0, 3, BOOKE_PAGESZ_4K, 1),
-
-#ifdef CONFIG_PCIE1
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 4, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_PCIE2
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_PCIE3
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 6, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 7, BOOKE_PAGESZ_64M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c
deleted file mode 100644
index 9089a0cc72..0000000000
--- a/board/xes/xpedite550x/xpedite550x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
-	/*
-	 * Remap NOR flash region to caching-inhibited
-	 * so that flash can be erased/programmed properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* Invalidate existing TLB entry for NOR flash */
-	disable_tlb(0);
-	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/zyxel/nsa310s/Kconfig b/board/zyxel/nsa310s/Kconfig
deleted file mode 100644
index 801d6966ea..0000000000
--- a/board/zyxel/nsa310s/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015
-# Gerald Kerma <dreagle@doukki.net>
-# Tony Dinh <mibodhi@gmail.com>
-
-if TARGET_NSA310S
-
-config SYS_BOARD
-	default "nsa310s"
-
-config SYS_VENDOR
-	default "zyxel"
-
-config SYS_CONFIG_NAME
-	default "nsa310s"
-
-endif
diff --git a/board/zyxel/nsa310s/MAINTAINERS b/board/zyxel/nsa310s/MAINTAINERS
deleted file mode 100644
index d153758c21..0000000000
--- a/board/zyxel/nsa310s/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-NSA310S BOARD
-M:	Gerald Kerma <dreagle@doukki.net>
-M:	Tony Dinh <mibodhi@gmail.com>
-M:	Luka Perkov <luka.perkov@sartura.hr>
-S:	Maintained
-F:	board/zyxel/nsa310s/
-F:	include/configs/nsa310s.h
-F:	configs/nsa310s_defconfig
diff --git a/board/zyxel/nsa310s/Makefile b/board/zyxel/nsa310s/Makefile
deleted file mode 100644
index 2131e28db3..0000000000
--- a/board/zyxel/nsa310s/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015
-# Gerald Kerma <dreagle@doukki.net>
-# Tony Dinh <mibodhi@gmail.com>
-
-obj-y	:= nsa310s.o
diff --git a/board/zyxel/nsa310s/kwbimage.cfg b/board/zyxel/nsa310s/kwbimage.cfg
deleted file mode 100644
index 9ebdeab94d..0000000000
--- a/board/zyxel/nsa310s/kwbimage.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015
-# Gerald Kerma <dreagle@doukki.net>
-# Tony Dinh <mibodhi@gmail.com>
-# Refer to doc/README.kwbimage for more details about how-to
-# configure and create kirkwood boot images.
-#
-
-# Boot Media configurations
-BOOT_FROM       nand
-NAND_ECC_MODE   default
-NAND_PAGE_SIZE  0x0800
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-DATA 0xFFD01400 0x43010c30
-DATA 0xFFD01404 0x39543000
-DATA 0xFFD01408 0x22125451
-DATA 0xFFD0140C 0x00000833
-DATA 0xFFD01410 0x0000000C
-DATA 0xFFD01414 0x00000000
-DATA 0xFFD01418 0x00000000
-DATA 0xFFD0141C 0x00000652
-DATA 0xFFD01420 0x00000004
-DATA 0xFFD01424 0x0000F17F
-DATA 0xFFD01428 0x00085520
-DATA 0xFFD0147c 0x00008552
-DATA 0xFFD01504 0x0FFFFFF1
-DATA 0xFFD01508 0x10000000
-DATA 0xFFD0150C 0x00000000
-DATA 0xFFD01514 0x00000000
-DATA 0xFFD0151C 0x00000000
-DATA 0xFFD01494 0x00010000
-DATA 0xFFD01498 0x00000000
-DATA 0xFFD0149C 0x0000E403
-DATA 0xFFD01480 0x00000001
-DATA 0xFFD20134 0x66666666
-DATA 0xFFD20138 0x66666666
-DATA 0x0 0x0
diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c
deleted file mode 100644
index cd4a7723b1..0000000000
--- a/board/zyxel/nsa310s/nsa310s.c
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015
- * Gerald Kerma <dreagle@doukki.net>
- * Tony Dinh <mibodhi@gmail.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <miiphy.h>
-#include <net.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include "nsa310s.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/*
-	 * default gpio configuration
-	 * There are maximum 64 gpios controlled through 2 sets of registers
-	 * the below configuration configures mainly initial LED status
-	 */
-	mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
-			  NSA310S_OE_LOW, NSA310S_OE_HIGH);
-
-	/* (all LEDs & power off active high) */
-	/* Multi-Purpose Pins Functionality configuration */
-	static const u32 kwmpp_config[] = {
-		MPP0_NF_IO2,
-		MPP1_NF_IO3,
-		MPP2_NF_IO4,
-		MPP3_NF_IO5,
-		MPP4_NF_IO6,
-		MPP5_NF_IO7,
-		MPP6_SYSRST_OUTn,
-		MPP7_GPO,
-		MPP8_TW_SDA,
-		MPP9_TW_SCK,
-		MPP10_UART0_TXD,
-		MPP11_UART0_RXD,
-		MPP12_GPO,
-		MPP13_GPIO,
-		MPP14_GPIO,
-		MPP15_GPIO,
-		MPP16_GPIO,
-		MPP17_GPIO,
-		MPP18_NF_IO0,
-		MPP19_NF_IO1,
-		MPP20_GPIO,
-		MPP21_GPIO,
-		MPP22_GPIO,
-		MPP23_GPIO,
-		MPP24_GPIO,
-		MPP25_GPIO,
-		MPP26_GPIO,
-		MPP27_GPIO,
-		MPP28_GPIO,
-		MPP29_GPIO,
-		MPP30_GPIO,
-		MPP31_GPIO,
-		MPP32_GPIO,
-		MPP33_GPIO,
-		MPP34_GPIO,
-		MPP35_GPIO,
-		0
-	};
-	kirkwood_mpp_conf(kwmpp_config, NULL);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
-	return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
-	u16 reg;
-	u16 phyaddr;
-	char *name = "egiga0";
-
-	if (miiphy_set_current_dev(name))
-		return;
-
-	/* read PHY dev address */
-	if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
-		printf("could not read PHY dev address\n");
-		return;
-	}
-
-	/* set RGMII delay */
-	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
-	miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg);
-	reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
-	miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
-	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
-
-	/* reset PHY */
-	if (miiphy_reset(name, phyaddr))
-		return;
-
-	/*
-	 * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
-	 * and has an MCU attached to the LED[2] via tristate interrupt
-	 */
-
-	/* switch to LED register page */
-	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
-	/* read out LED polarity register */
-	miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, &reg);
-	/* clear 4, set 5 - LED2 low, tri-state */
-	reg &= ~(MV88E1318_LED2_4);
-	reg |= (MV88E1318_LED2_5);
-	/* write back LED polarity register */
-	miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
-	/* jump back to page 0, per the PHY chip documenation. */
-	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
-
-	/* set PHY back to auto-negotiation mode */
-	miiphy_write(name, phyaddr, 0x4, 0x1e1);
-	miiphy_write(name, phyaddr, 0x9, 0x300);
-	/* downshift */
-	miiphy_write(name, phyaddr, 0x10, 0x3860);
-	miiphy_write(name, phyaddr, 0x0, 0x9140);
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/zyxel/nsa310s/nsa310s.h b/board/zyxel/nsa310s/nsa310s.h
deleted file mode 100644
index d8bd9a586f..0000000000
--- a/board/zyxel/nsa310s/nsa310s.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015
- * Gerald Kerma <dreagle@doukki.net>
- * Tony Dinh <mibodhi@gmail.com>
- */
-
-#ifndef __NSA310S_H
-#define __NSA310S_H
-
-/* low GPIO's */
-#define HDD1_GREEN_LED		(1 << 16)
-#define HDD1_RED_LED		(1 << 13)
-#define USB_GREEN_LED		(1 << 15)
-#define USB_POWER			(1 << 21)
-#define SYS_GREEN_LED		(1 << 28)
-#define SYS_ORANGE_LED		(1 << 29)
-
-#define COPY_GREEN_LED		(1 << 22)
-#define COPY_RED_LED		(1 << 23)
-
-#define PIN_USB_GREEN_LED	15
-#define PIN_USB_POWER		21
-
-#define NSA310S_OE_LOW		(~(0))
-#define NSA310S_VAL_LOW		(SYS_GREEN_LED | USB_POWER)
-
-/* high GPIO's */
-#define HDD2_GREEN_LED		(1 << 2)
-#define HDD2_POWER			(1 << 1)
-
-#define NSA310S_OE_HIGH		(~(0))
-#define NSA310S_VAL_HIGH	(HDD2_POWER)
-
-/* PHY related */
-#define MV88E1318_PGADR_REG		22
-#define MV88E1318_MAC_CTRL_PG	2
-#define MV88E1318_MAC_CTRL_REG	21
-#define MV88E1318_RGMII_TX_CTRL	(1 << 4)
-#define MV88E1318_RGMII_RX_CTRL	(1 << 5)
-#define MV88E1318_LED_PG		3
-#define MV88E1318_LED_POL_REG	17
-#define MV88E1318_LED2_4		(1 << 4)
-#define MV88E1318_LED2_5		(1 << 5)
-
-#endif /* __NSA310S_H */
author	Tom Rini <trini@konsulko.com>	2021-07-07 22:50:41 -0400
committer	Tom Rini <trini@konsulko.com>	2021-07-07 22:50:41 -0400
commit	bfb5bfa3c58adc2ef5dbd1bb95b79b31e0dc221c (patch)
tree	21753c7f94144a286584c1f631ad9bde89a1a438 /board
parent	7e58a3a148fb94e9ce09fb48d0ddd75c20ee7df9 (diff)
parent	123dc510c6e79f0c94718e2e6b5e4074754aa629 (diff)
download	u-boot-bfb5bfa3c58adc2ef5dbd1bb95b79b31e0dc221c.tar.gz