diff options
| author | Tom Rini <trini@konsulko.com> | 2017-03-19 14:49:26 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-03-19 15:13:38 -0400 |
| commit | 02ccab1908c405fe1449457d4a0d343784a30acb (patch) | |
| tree | 3a5d41abff96a3af22587ace67713d5c0165b097 /board | |
| parent | f40574e2d78c96a3818c4fa2379382d924866a6e (diff) | |
| parent | d883fcc6bbb2fcc3df90857fee99c2f543a0289c (diff) | |
| download | u-boot-02ccab1908c405fe1449457d4a0d343784a30acb.tar.gz | |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
configs/bk4r1_defconfig
configs/colibri_vf_defconfig
configs/pcm052_defconfig
include/configs/colibri_vf.h
include/configs/pcm052.h
Diffstat (limited to 'board')
33 files changed, 1520 insertions, 122 deletions
diff --git a/board/armadeus/opos6uldev/Kconfig b/board/armadeus/opos6uldev/Kconfig new file mode 100644 index 0000000000..beca37dfb3 --- /dev/null +++ b/board/armadeus/opos6uldev/Kconfig @@ -0,0 +1,15 @@ +if TARGET_OPOS6ULDEV + +config SYS_BOARD + default "opos6uldev" + +config SYS_VENDOR + default "armadeus" + +config SYS_CONFIG_NAME + default "opos6uldev" + +config IMX_CONFIG + default "arch/arm/imx-common/spl_sd.cfg" + +endif diff --git a/board/armadeus/opos6uldev/MAINTAINERS b/board/armadeus/opos6uldev/MAINTAINERS new file mode 100644 index 0000000000..e46c66942d --- /dev/null +++ b/board/armadeus/opos6uldev/MAINTAINERS @@ -0,0 +1,6 @@ +OPOS6ULDev BOARD +M: Sébastien Szymanski <sebastien.szymanski@armadeus.com> +S: Maintained +F: board/armadeus/opos6uldev/ +F: include/configs/opos6uldev.h +F: configs/opos6uldev_defconfig diff --git a/board/armadeus/opos6uldev/Makefile b/board/armadeus/opos6uldev/Makefile new file mode 100644 index 0000000000..fd14fd75a6 --- /dev/null +++ b/board/armadeus/opos6uldev/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2017 Armadeus Systems +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/armadeus/opos6uldev/board.c b/board/armadeus/opos6uldev/board.c new file mode 100644 index 0000000000..500d0bd2df --- /dev/null +++ b/board/armadeus/opos6uldev/board.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2017 Armadeus Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/opos6ul.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_VIDEO_MXS +#define LCD_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm \ +) + +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +int setup_lcd(void) +{ + struct gpio_desc backlight; + int ret; + + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Set Brightness to high */ + ret = dm_gpio_lookup_name("GPIO4_10", &backlight); + if (ret) { + printf("Cannot get GPIO4_10\n"); + return ret; + } + + ret = dm_gpio_request(&backlight, "backlight"); + if (ret) { + printf("Cannot request GPIO4_10\n"); + return ret; + } + + dm_gpio_set_dir_flags(&backlight, GPIOD_IS_OUT); + dm_gpio_set_value(&backlight, 1); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int opos6ul_board_late_init(void) +{ +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#define UART_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \ +) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +void opos6ul_setup_uart_debug(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/engicam/geam6ul/MAINTAINERS b/board/engicam/geam6ul/MAINTAINERS index 079370ccb9..1c31375395 100644 --- a/board/engicam/geam6ul/MAINTAINERS +++ b/board/engicam/geam6ul/MAINTAINERS @@ -5,3 +5,4 @@ F: board/engicam/geam6ul F: include/configs/imx6ul_geam.h F: configs/imx6ul_geam_mmc_defconfig F: configs/imx6ul_geam_nand_defconfig +F: arch/arm/dts/imx6ul-geam-kit.dts diff --git a/board/engicam/icorem6/MAINTAINERS b/board/engicam/icorem6/MAINTAINERS index 0ef3a2c97e..6116648e37 100644 --- a/board/engicam/icorem6/MAINTAINERS +++ b/board/engicam/icorem6/MAINTAINERS @@ -7,3 +7,6 @@ F: configs/imx6q_icore_mmc_defconfig F: configs/imx6q_icore_nand_defconfig F: configs/imx6dl_icore_mmc_defconfig F: configs/imx6dl_icore_nand_defconfig +F: arch/arm/dts/imx6qdl-icore.dtsi +F: arch/arm/dts/imx6q-icore.dts +F: arch/arm/dts/imx6dl-icore.dts diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS index 0556211862..2d2295c3c5 100644 --- a/board/engicam/icorem6_rqs/MAINTAINERS +++ b/board/engicam/icorem6_rqs/MAINTAINERS @@ -5,3 +5,6 @@ F: board/engicam/icorem6_rqs F: include/configs/imx6qdl_icore_rqs.h F: configs/imx6q_icore_rqs_mmc_defconfig F: configs/imx6dl_icore_rqs_mmc_defconfig +F: arch/arm/dts/imx6qdl-icore-rqs.dtsi +F: arch/arm/dts/imx6q-icore-rqs.dts +F: arch/arm/dts/imx6dl-icore-rqs.dts diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c index 2769177dd3..01380f1269 100644 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <mmc.h> #include <asm/io.h> #include <asm/gpio.h> @@ -45,6 +46,51 @@ int board_init(void) return 0; } +#ifdef CONFIG_ENV_IS_IN_MMC +int board_mmc_get_env_dev(int devno) +{ + /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */ + return (devno == 3) ? 1 : 0; +} + +static void mmc_late_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +int board_late_init(void) +{ + switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> + IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: +#ifdef CONFIG_ENV_IS_IN_MMC + mmc_late_init(); +#endif + setenv("modeboot", "mmcboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -77,8 +123,22 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; -struct fsl_esdhc_cfg usdhc_cfg[1] = { +static iomux_v3_cfg_t const usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR, 1, 4}, + {USDHC4_BASE_ADDR, 1, 8}, }; int board_mmc_getcd(struct mmc *mmc) @@ -88,6 +148,7 @@ int board_mmc_getcd(struct mmc *mmc) switch (cfg->esdhc_base) { case USDHC3_BASE_ADDR: + case USDHC4_BASE_ADDR: ret = 1; break; } @@ -102,7 +163,8 @@ int board_mmc_init(bd_t *bis) /* * According to the board_mmc_init() the following map is done: * (U-boot device node) (Physical Port) - * mmc0 USDHC3 + * mmc0 USDHC3 + * mmc1 USDHC4 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { @@ -110,6 +172,10 @@ int board_mmc_init(bd_t *bis) SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; + case 1: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; default: printf("Warning - USDHC%d controller not supporting\n", i + 1); @@ -125,6 +191,32 @@ int board_mmc_init(bd_t *bis) return 0; } + +#ifdef CONFIG_ENV_IS_IN_MMC +void board_boot_order(u32 *spl_boot_list) +{ + u32 bmode = imx6_src_get_boot_mode(); + u8 boot_dev = BOOT_DEVICE_MMC1; + + switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + /* SD/eSD - BOOT_DEVICE_MMC1 */ + break; + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* MMC/eMMC */ + boot_dev = BOOT_DEVICE_MMC2; + break; + default: + /* Default - BOOT_DEVICE_MMC1 */ + printf("Wrong board boot order\n"); + break; + } + + spl_boot_list[0] = boot_dev; +} +#endif #endif /* diff --git a/board/engicam/isiotmx6ul/Kconfig b/board/engicam/isiotmx6ul/Kconfig new file mode 100644 index 0000000000..213ffad8b6 --- /dev/null +++ b/board/engicam/isiotmx6ul/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6UL_ISIOT + +config SYS_BOARD + default "isiotmx6ul" + +config SYS_VENDOR + default "engicam" + +config SYS_CONFIG_NAME + default "imx6ul_isiot" + +endif diff --git a/board/engicam/isiotmx6ul/MAINTAINERS b/board/engicam/isiotmx6ul/MAINTAINERS new file mode 100644 index 0000000000..c30cfe7c7d --- /dev/null +++ b/board/engicam/isiotmx6ul/MAINTAINERS @@ -0,0 +1,12 @@ +ISIOTMX6UL BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: board/engicam/isiotmx6ul +F: include/configs/imx6ul_isiot.h +F: configs/imx6ul_isiot_mmc_defconfig +F: configs/imx6ul_isiot_emmc_defconfig +F: configs/imx6ul_isiot_nand_defconfig +F: arch/arm/dts/imx6ul-isiot.dtsi +F: arch/arm/dts/imx6ul-isiot-mmc.dts +F: arch/arm/dts/imx6ul-isiot-emmc.dts +F: arch/arm/dts/imx6ul-isiot-nand.dts diff --git a/board/engicam/isiotmx6ul/Makefile b/board/engicam/isiotmx6ul/Makefile new file mode 100644 index 0000000000..f4f8c780ae --- /dev/null +++ b/board/engicam/isiotmx6ul/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2016 Amarula Solutions B.V. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := isiotmx6ul.o diff --git a/board/engicam/isiotmx6ul/README b/board/engicam/isiotmx6ul/README new file mode 100644 index 0000000000..1d177ac625 --- /dev/null +++ b/board/engicam/isiotmx6ul/README @@ -0,0 +1,28 @@ +How to use U-Boot on Engicam Is.IoT MX6UL Starter Kit: +----------------------------------------------------- + +- Configure U-Boot for Engicam Is.IoT MX6UL + +$ make mrproper +$ make imx6ul_isiot_mmc_defconfig +$ make + +This will generate the SPL image called SPL and the u-boot-dtb.img. + +- Flash the SPL image into the micro SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot-dtb.img image into the micro SD card: + +sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Jumper settings: + +MMC Boot: JM3 Closed + +- Connect the Serial cable between the Starter Kit and the PC for the console. +(J28 is the Linux Serial console connector) + +- Insert the micro SD card in the board, power it up and U-Boot messages should +come up. diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c new file mode 100644 index 0000000000..29a137dc81 --- /dev/null +++ b/board/engicam/isiotmx6ul/isiotmx6ul.c @@ -0,0 +1,414 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * Author: Jagan Teki <jagan@amarulasolutions.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mmc.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/sizes.h> + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/iomux-v3.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + + return 0; +} + +#ifdef CONFIG_NAND_MXS + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif /* CONFIG_NAND_MXS */ + +#ifdef CONFIG_ENV_IS_IN_MMC +int board_mmc_get_env_dev(int devno) +{ + /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */ + return (devno == 0) ? 0 : 1; +} + +static void mmc_late_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +int board_late_init(void) +{ + switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> + IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: +#ifdef CONFIG_ENV_IS_IN_MMC + mmc_late_init(); +#endif + setenv("modeboot", "mmcboot"); + break; + case IMX6_BMODE_NAND: + setenv("modeboot", "nandboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include <libfdt.h> +#include <spl.h> + +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-ddr.h> + +/* MMC board initialization is needed till adding DM support in SPL */ +#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) +#include <mmc.h> +#include <fsl_esdhc.h> + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) + +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 4}, + {USDHC2_BASE_ADDR, 0, 8}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +#ifdef CONFIG_ENV_IS_IN_MMC +void board_boot_order(u32 *spl_boot_list) +{ + u32 bmode = imx6_src_get_boot_mode(); + u8 boot_dev = BOOT_DEVICE_MMC1; + + switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + /* SD/eSD - BOOT_DEVICE_MMC1 */ + break; + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* MMC/eMMC */ + boot_dev = BOOT_DEVICE_MMC2; + break; + default: + /* Default - BOOT_DEVICE_MMC1 */ + printf("Wrong board boot order\n"); + break; + } + + spl_boot_list[0] = boot_dev; +} +#endif +#endif /* CONFIG_FSL_ESDHC */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00070007, + .p0_mpdgctrl0 = 0x41490145, + .p0_mprddlctl = 0x40404546, + .p0_mpwrdlctl = 0x4040524D, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00c03f3f, &ccm->CCGR0); + writel(0xfcffff00, &ccm->CCGR1); + writel(0x0cffffcc, &ccm->CCGR2); + writel(0x3f3c3030, &ccm->CCGR3); + writel(0xff00fffc, &ccm->CCGR4); + writel(0x033f30ff, &ccm->CCGR5); + writel(0x00c00fff, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/freescale/mx7ulp_evk/Kconfig b/board/freescale/mx7ulp_evk/Kconfig new file mode 100644 index 0000000000..ff448311f9 --- /dev/null +++ b/board/freescale/mx7ulp_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX7ULP_EVK + +config SYS_BOARD + default "mx7ulp_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7ulp_evk" + +endif diff --git a/board/freescale/mx7ulp_evk/MAINTAINERS b/board/freescale/mx7ulp_evk/MAINTAINERS new file mode 100644 index 0000000000..1aa2644563 --- /dev/null +++ b/board/freescale/mx7ulp_evk/MAINTAINERS @@ -0,0 +1,7 @@ +MX7ULPEVK BOARD +M: Peng Fan <peng.fan@nxp.com> +S: Maintained +F: board/freescale/mx7ulp_evk/ +F: include/configs/mx7ulp_evk.h +F: configs/mx7ulp_evk_defconfig +F: configs/mx7ulp_evk_plugin_defconfig diff --git a/board/freescale/mx7ulp_evk/Makefile b/board/freescale/mx7ulp_evk/Makefile new file mode 100644 index 0000000000..5e19eb4859 --- /dev/null +++ b/board/freescale/mx7ulp_evk/Makefile @@ -0,0 +1,10 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7ulp_evk.o + +extra-$(CONFIG_USE_PLUGIN) := plugin.bin +$(obj)/plugin.bin: $(obj)/plugin.o + $(OBJCOPY) -O binary --gap-fill 0xff $< $@ diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg new file mode 100644 index 0000000000..e4e4cb3b21 --- /dev/null +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x403f00dc 0x00000000 +DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808080 +DATA 4 0x403e0508 0x00140000 +DATA 4 0x403E0510 0x00000004 +DATA 4 0x403E0514 0x00000002 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x8080801E +CHECK_BITS_SET 4 0x403e050c 0x00000040 +DATA 4 0x403E0030 0x00000001 +DATA 4 0x403e0040 0x11000020 +DATA 4 0x403f00dc 0x42000000 + +DATA 4 0x40B300AC 0x40000000 + +DATA 4 0x40AD0128 0x00040000 +DATA 4 0x40AD00F8 0x00000000 +DATA 4 0x40AD00D8 0x00000180 +DATA 4 0x40AD0108 0x00000180 +DATA 4 0x40AD0104 0x00000180 +DATA 4 0x40AD0124 0x00010000 +DATA 4 0x40AD0080 0x0000018C +DATA 4 0x40AD0084 0x0000018C +DATA 4 0x40AD0088 0x0000018C +DATA 4 0x40AD008C 0x0000018C + +DATA 4 0x40AD0120 0x00010000 +DATA 4 0x40AD010C 0x00000180 +DATA 4 0x40AD0110 0x00000180 +DATA 4 0x40AD0114 0x00000180 +DATA 4 0x40AD0118 0x00000180 +DATA 4 0x40AD0090 0x00000180 +DATA 4 0x40AD0094 0x00000180 +DATA 4 0x40AD0098 0x00000180 +DATA 4 0x40AD009C 0x00000180 + +DATA 4 0x40AD00E0 0x00040000 +DATA 4 0x40AD00E4 0x00040000 + +DATA 4 0x40AB001C 0x00008000 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB085C 0x0D3900A0 +DATA 4 0x40AB0890 0x00400000 + +DATA 4 0x40AB0848 0x40404040 +DATA 4 0x40AB0850 0x40404040 +DATA 4 0x40AB081C 0x33333333 +DATA 4 0x40AB0820 0x33333333 +DATA 4 0x40AB0824 0x33333333 +DATA 4 0x40AB0828 0x33333333 + +DATA 4 0x40AB082C 0xf3333333 +DATA 4 0x40AB0830 0xf3333333 +DATA 4 0x40AB0834 0xf3333333 +DATA 4 0x40AB0838 0xf3333333 + +DATA 4 0x40AB08C0 0x24922492 +DATA 4 0x40AB08B8 0x00000800 + +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB000C 0x292C42F3 +DATA 4 0x40AB0010 0x00100A22 +DATA 4 0x40AB0038 0x00120556 +DATA 4 0x40AB0014 0x00C700DB +DATA 4 0x40AB0018 0x00211718 +DATA 4 0x40AB002C 0x0F9F26D2 +DATA 4 0x40AB0030 0x009F0E10 +DATA 4 0x40AB0040 0x0000003F +DATA 4 0x40AB0000 0xC3190000 + +DATA 4 0x40AB001C 0x00008050 +DATA 4 0x40AB001C 0x00008058 +DATA 4 0x40AB001C 0x003F8030 +DATA 4 0x40AB001C 0x003F8038 +DATA 4 0x40AB001C 0xFF0A8030 +DATA 4 0x40AB001C 0xFF0A8038 +DATA 4 0x40AB001C 0x04028030 +DATA 4 0x40AB001C 0x04028038 +DATA 4 0x40AB001C 0x83018030 +DATA 4 0x40AB001C 0x83018038 +DATA 4 0x40AB001C 0x01038030 +DATA 4 0x40AB001C 0x01038038 + +DATA 4 0x40AB083C 0x20000000 + +DATA 4 0x40AB0020 0x00001800 +DATA 4 0x40AB0800 0xA1310000 +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB0404 0x00011006 +DATA 4 0x40AB001C 0x00000000 +#endif diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c new file mode 100644 index 0000000000..361871525e --- /dev/null +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mx7ulp-pins.h> +#include <asm/arch/iomux.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_UP) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_cfg_t const lpuart4_pads[] = { + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, + ARRAY_SIZE(lpuart4_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S new file mode 100644 index 0000000000..9eab36520a --- /dev/null +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +.macro imx7ulp_ddr_freq_decrease + ldr r2, =0x403f0000 + ldr r3, =0x00000000 + str r3, [r2, #0xdc] + + ldr r2, =0x403e0000 + ldr r3, =0x01000020 + str r3, [r2, #0x40] + ldr r3, =0x01000000 + str r3, [r2, #0x500] + ldr r3, =0x80808080 + str r3, [r2, #0x50c] + ldr r3, =0x00140000 + str r3, [r2, #0x508] + ldr r3, =0x00000004 + str r3, [r2, #0x510] + ldr r3, =0x00000002 + str r3, [r2, #0x514] + ldr r3, =0x00000001 + str r3, [r2, #0x500] + + ldr r3, =0x01000000 +wait1: + ldr r4, [r2, #0x500] + and r4, r3 + cmp r4, r3 + bne wait1 + + ldr r3, =0x8080801E + str r3, [r2, #0x50c] + + ldr r3, =0x00000040 +wait2: + ldr r4, [r2, #0x50c] + and r4, r3 + cmp r4, r3 + bne wait2 + + ldr r3, =0x00000001 + str r3, [r2, #0x30] + ldr r3, =0x11000020 + str r3, [r2, #0x40] + + ldr r2, =0x403f0000 + ldr r3, =0x42000000 + str r3, [r2, #0xdc] + +.endm + +.macro imx7ulp_evk_ddr_setting + + imx7ulp_ddr_freq_decrease + + /* Enable MMDC PCC clock */ + ldr r2, =0x40b30000 + ldr r3, =0x40000000 + str r3, [r2, #0xac] + + /* Configure DDR pad */ + ldr r0, =0x40ad0000 + ldr r1, =0x00040000 + str r1, [r0, #0x128] + ldr r1, =0x0 + str r1, [r0, #0xf8] + ldr r1, =0x00000180 + str r1, [r0, #0xd8] + ldr r1, =0x00000180 + str r1, [r0, #0x108] + ldr r1, =0x00000180 + str r1, [r0, #0x104] + ldr r1, =0x00010000 + str r1, [r0, #0x124] + ldr r1, =0x0000018C + str r1, [r0, #0x80] + ldr r1, =0x0000018C + str r1, [r0, #0x84] + ldr r1, =0x0000018C + str r1, [r0, #0x88] + ldr r1, =0x0000018C + str r1, [r0, #0x8c] + + ldr r1, =0x00010000 + str r1, [r0, #0x120] + ldr r1, =0x00000180 + str r1, [r0, #0x10c] + ldr r1, =0x00000180 + str r1, [r0, #0x110] + ldr r1, =0x00000180 + str r1, [r0, #0x114] + ldr r1, =0x00000180 + str r1, [r0, #0x118] + ldr r1, =0x00000180 + str r1, [r0, #0x90] + ldr r1, =0x00000180 + str r1, [r0, #0x94] + ldr r1, =0x00000180 + str r1, [r0, #0x98] + ldr r1, =0x00000180 + str r1, [r0, #0x9c] + ldr r1, =0x00040000 + str r1, [r0, #0xe0] + ldr r1, =0x00040000 + str r1, [r0, #0xe4] + + ldr r0, =0x40ab0000 + ldr r1, =0x00008000 + str r1, [r0, #0x1c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0D3900A0 + str r1, [r0, #0x85c] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x40404040 + str r1, [r0, #0x848] + ldr r1, =0x40404040 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81c] + ldr r1, =0x33333333 + str r1, [r0, #0x820] + ldr r1, =0x33333333 + str r1, [r0, #0x824] + ldr r1, =0x33333333 + str r1, [r0, #0x828] + + ldr r1, =0xf3333333 + str r1, [r0, #0x82c] + ldr r1, =0xf3333333 + str r1, [r0, #0x830] + ldr r1, =0xf3333333 + str r1, [r0, #0x834] + ldr r1, =0xf3333333 + str r1, [r0, #0x838] + + ldr r1, =0x24922492 + str r1, [r0, #0x8c0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x292C42F3 + str r1, [r0, #0xc] + ldr r1, =0x00100A22 + str r1, [r0, #0x10] + ldr r1, =0x00120556 + str r1, [r0, #0x38] + ldr r1, =0x00C700DB + str r1, [r0, #0x14] + ldr r1, =0x00211718 + str r1, [r0, #0x18] + + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x2c] + ldr r1, =0x009F0E10 + str r1, [r0, #0x30] + ldr r1, =0x0000003F + str r1, [r0, #0x40] + ldr r1, =0xC3190000 + str r1, [r0, #0x0] + + ldr r1, =0x00008050 + str r1, [r0, #0x1c] + ldr r1, =0x00008058 + str r1, [r0, #0x1c] + ldr r1, =0x003F8030 + str r1, [r0, #0x1c] + ldr r1, =0x003F8038 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x1c] + ldr r1, =0x04028030 + str r1, [r0, #0x1c] + ldr r1, =0x04028038 + str r1, [r0, #0x1c] + ldr r1, =0x83018030 + str r1, [r0, #0x1c] + ldr r1, =0x83018038 + str r1, [r0, #0x1c] + ldr r1, =0x01038030 + str r1, [r0, #0x1c] + ldr r1, =0x01038038 + str r1, [r0, #0x1c] + + ldr r1, =0x20000000 + str r1, [r0, #0x83c] + + ldr r1, =0x00001800 + str r1, [r0, #0x20] + ldr r1, =0xA1310000 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x1c] + +.endm + +.macro imx7ulp_clock_gating +.endm + +.macro imx7ulp_qos_setting +.endm + +.macro imx7ulp_ddr_setting + imx7ulp_evk_ddr_setting +.endm + +/* include the common plugin code here */ +#include <asm/arch/mx7ulp_plugin.S> diff --git a/board/freescale/vf610twr/Kconfig b/board/freescale/vf610twr/Kconfig index ef091d6b2b..3b90ed67fe 100644 --- a/board/freescale/vf610twr/Kconfig +++ b/board/freescale/vf610twr/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "freescale" -config SYS_SOC - default "vf610" - config SYS_CONFIG_NAME default "vf610twr" diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README index f3f8998aae..57c64a1b2a 100644 --- a/board/gateworks/gw_ventana/README +++ b/board/gateworks/gw_ventana/README @@ -30,7 +30,12 @@ will build the following artifacts from U-Boot source: To build U-Boot for the Gateworks Ventana product family: - make gwventana_config +For NAND FLASH based boards: + make gwventana_nand_config + make + +For EMMC FLASH based boards: + make gwventana_emmc_config make @@ -99,11 +104,11 @@ This information is taken from: More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual. -3.1. boot from micro-SD ------------------------ +3.1. boot from MMC (eMMC/microSD) +--------------------------------- When the IMX6 eFUSE settings have been factory programmed to boot from -micro-SD the SPL will be loaded from offset 0x400 (1KB). Once the SPL is +MMC the SPL will be loaded from offset 0x400 (1KB). Once the SPL is booted, it will load and execute U-Boot (u-boot.img) from offset 69KB on the micro-SD (defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR). @@ -111,11 +116,11 @@ While it is technically possible to enable the SPL to be able to load U-Boot from a file on a FAT/EXT filesystem on the micro-SD, we chose to use raw micro-SD access to keep the code-size and boot time of the SPL down. -For these reasons a micro-SD that will be used as an IMX6 primary boot +For these reasons an MMC device that will be used as an IMX6 primary boot device must be carefully partitioned and prepared. The following shell commands are executed on a Linux host (adjust DEV to the -block storage device of your micro-SD): +block storage device of your MMC, ie /dev/mmcblk0): DEV=/dev/sdc # zero out 1MB of device diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 4065c5655a..3dc5f88102 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -6,10 +6,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <asm/arch/clock.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/imx-common/mxc_i2c.h> +#include <fsl_esdhc.h> #include <hwconfig.h> #include <power/pmic.h> #include <power/ltc3676_pmic.h> @@ -35,6 +37,17 @@ void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart2_pads); } +/* MMC */ +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + /* I2C1: GSC */ static struct i2c_pads_info mx6q_i2c_pad_info0 = { .scl = { @@ -130,12 +143,6 @@ void setup_ventana_i2c(void) * Baseboard specific GPIO */ -/* common to add baseboards */ -static iomux_v3_cfg_t const gw_gpio_pads[] = { - /* SD3_VSELECT */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), -}; - /* prototype */ static iomux_v3_cfg_t const gwproto_gpio_pads[] = { /* RS232_EN# */ @@ -183,6 +190,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { }; static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { + /* SD3_VSELECT */ + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), /* RS232_EN# */ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* MSATA_EN */ @@ -216,6 +225,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { }; static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* SD3_VSELECT */ + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), /* RS232_EN# */ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* MSATA_EN */ @@ -249,6 +260,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { }; static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* SD3_VSELECT */ + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), /* RS232_EN# */ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* MSATA_EN */ @@ -325,11 +338,12 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = { }; static iomux_v3_cfg_t const gw553x_gpio_pads[] = { + /* SD3_VSELECT */ + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), /* PANLEDR# */ IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG), - /* VID_PWR */ IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), /* PCI_RST# */ @@ -573,6 +587,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .rs485en = IMX_GPIO_NR(3, 24), .dioi2c_en = IMX_GPIO_NR(4, 5), .pcie_sson = IMX_GPIO_NR(1, 20), + .otgpwr_en = IMX_GPIO_NR(3, 22), }, /* GW51xx */ @@ -591,6 +606,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .gps_shdn = IMX_GPIO_NR(1, 2), .vidin_en = IMX_GPIO_NR(5, 20), .wdis = IMX_GPIO_NR(7, 12), + .otgpwr_en = IMX_GPIO_NR(3, 22), }, /* GW52xx */ @@ -613,6 +629,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, .rs232_en = GP_RS232_EN, + .otgpwr_en = IMX_GPIO_NR(3, 22), + .vsel_pin = IMX_GPIO_NR(6, 14), }, /* GW53xx */ @@ -634,6 +652,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, .rs232_en = GP_RS232_EN, + .otgpwr_en = IMX_GPIO_NR(3, 22), + .vsel_pin = IMX_GPIO_NR(6, 14), }, /* GW54xx */ @@ -657,6 +677,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .wdis = IMX_GPIO_NR(5, 17), .msata_en = GP_MSATA_SEL, .rs232_en = GP_RS232_EN, + .otgpwr_en = IMX_GPIO_NR(3, 22), + .vsel_pin = IMX_GPIO_NR(6, 14), }, /* GW551x */ @@ -702,6 +724,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .pcie_rst = IMX_GPIO_NR(1, 0), .vidin_en = IMX_GPIO_NR(5, 20), .wdis = IMX_GPIO_NR(7, 12), + .otgpwr_en = IMX_GPIO_NR(3, 22), + .vsel_pin = IMX_GPIO_NR(6, 14), }, }; @@ -709,13 +733,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) { int i; - /* iomux common to all Ventana boards */ - SETUP_IOMUX_PADS(gw_gpio_pads); - - /* OTG power off */ - gpio_request(GP_USB_OTG_PWR, "usbotg_pwr"); - gpio_direction_output(GP_USB_OTG_PWR, 0); - if (board >= GW_UNKNOWN) return; @@ -725,7 +742,7 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) /* RS232_EN# */ if (gpio_cfg[board].rs232_en) { - gpio_request(gpio_cfg[board].rs232_en, "rs232_en"); + gpio_request(gpio_cfg[board].rs232_en, "rs232_en#"); gpio_direction_output(gpio_cfg[board].rs232_en, 0); } @@ -805,10 +822,18 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) gpio_direction_output(gpio_cfg[board].wdis, 1); } + /* OTG power off */ + if (gpio_cfg[board].otgpwr_en) { + gpio_request(gpio_cfg[board].otgpwr_en, "usbotg_pwr"); + gpio_direction_output(gpio_cfg[board].otgpwr_en, 0); + } + /* sense vselect pin to see if we support uhs-i */ - gpio_request(GP_SD3_VSELECT, "sd3_vselect"); - gpio_direction_input(GP_SD3_VSELECT); - gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT); + if (gpio_cfg[board].vsel_pin) { + gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect"); + gpio_direction_input(gpio_cfg[board].vsel_pin); + gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin); + } } /* setup GPIO pinmux and default configuration per baseboard and env */ @@ -964,3 +989,25 @@ void setup_pmic(void) } } } + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; + +int board_mmc_init(bd_t *bis) +{ + /* Only one USDHC controller on Ventana */ + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg.max_bus_width = 4; + + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + /* Card Detect */ + gpio_request(GP_SD3_CD, "sd_cd"); + gpio_direction_input(GP_SD3_CD); + return !gpio_get_value(GP_SD3_CD); +} +#endif /* CONFIG_FSL_ESDHC */ diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index 3d7aff1077..18909a02b5 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -13,11 +13,9 @@ /* GPIO's common to all baseboards */ #define GP_PHY_RST IMX_GPIO_NR(1, 30) -#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) #define GP_SD3_CD IMX_GPIO_NR(7, 0) #define GP_RS232_EN IMX_GPIO_NR(2, 11) #define GP_MSATA_SEL IMX_GPIO_NR(2, 8) -#define GP_SD3_VSELECT IMX_GPIO_NR(6, 14) #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ @@ -79,6 +77,8 @@ struct ventana { int wdis; int msata_en; int rs232_en; + int otgpwr_en; + int vsel_pin; /* various features */ bool usd_vsel; }; diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 5d871ceed9..3f9d2f7010 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -52,17 +52,6 @@ struct ventana_board_info ventana_info; static int board_type; -/* MMC */ -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - /* ENET */ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), @@ -186,35 +175,15 @@ int board_ehci_hcd_init(int port) int board_ehci_power(int port, int on) { - if (port) - return 0; - gpio_set_value(GP_USB_OTG_PWR, on); + /* enable OTG VBUS */ + if (!port && board_type < GW_UNKNOWN) { + if (gpio_cfg[board_type].otgpwr_en) + gpio_set_value(gpio_cfg[board_type].otgpwr_en, on); + } return 0; } #endif /* CONFIG_USB_EHCI_MX6 */ -#ifdef CONFIG_FSL_ESDHC -static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* Card Detect */ - gpio_request(GP_SD3_CD, "sd_cd"); - gpio_direction_input(GP_SD3_CD); - return !gpio_get_value(GP_SD3_CD); -} - -int board_mmc_init(bd_t *bis) -{ - /* Only one USDHC controller on Ventana */ - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg.max_bus_width = 4; - - return fsl_esdhc_initialize(bis, &usdhc_cfg); -} -#endif /* CONFIG_FSL_ESDHC */ - #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ @@ -772,7 +741,7 @@ int misc_init_r(void) /* Set a non-initialized hwconfig based on board configuration */ if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) { - sprintf(buf, "hwconfig="); + buf[0] = 0; if (gpio_cfg[board_type].rs232_en) strcat(buf, "rs232;"); for (i = 0; i < gpio_cfg[board_type].dio_num; i++) { diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index b610e06f1d..8cc2a571d3 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -355,6 +355,25 @@ static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { .p1_mpwrdlctl = 0X40304239, }; +static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x0048004A, + .p0_mpwldectrl1 = 0x003F004A, + .p1_mpwldectrl0 = 0x001E0028, + .p1_mpwldectrl1 = 0x002C0043, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x02250219, + .p0_mpdgctrl1 = 0x01790202, + .p1_mpdgctrl0 = 0x02080208, + .p1_mpdgctrl1 = 0x016C0175, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x4A4C4D4C, + .p1_mprddlctl = 0x494C4A48, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x403F3437, + .p1_mpwrdlctl = 0x383A3930, +}; + static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x002A0025, @@ -368,6 +387,25 @@ static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = { .p0_mpwrdlctl = 0x303E3C36, }; +static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00230020, + .p0_mpwldectrl1 = 0x002F002A, + .p1_mpwldectrl0 = 0x001D0027, + .p1_mpwldectrl1 = 0x00100023, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x03250339, + .p0_mpdgctrl1 = 0x031C0316, + .p1_mpdgctrl0 = 0x03210331, + .p1_mpdgctrl1 = 0x031C025A, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x40373C40, + .p1_mprddlctl = 0x3A373646, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x2E353933, + .p1_mpwrdlctl = 0x3C2F3F35, +}; + static void spl_dram_init(int width, int size_mb, int board_model) { struct mx6_ddr3_cfg *mem = NULL; @@ -468,7 +506,14 @@ static void spl_dram_init(int width, int size_mb, int board_model) mem = &mt41k256m16ha_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_256x64_mmdc_calib; + else + calib = &mx6sdl_256x64_mmdc_calib; debug("4gB density\n"); + } else if (width == 64 && size_mb == 4096) { + mem = &mt41k512m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_512x64_mmdc_calib; + debug("8gB density\n"); } if (!(mem && calib)) { diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig index 212f994294..4fde21c586 100644 --- a/board/phytec/pcm052/Kconfig +++ b/board/phytec/pcm052/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "phytec" -config SYS_SOC - default "vf610" - config SYS_CONFIG_NAME default "pcm052" @@ -26,9 +23,6 @@ config SYS_BOARD config SYS_VENDOR default "phytec" -config SYS_SOC - default "vf610" - config SYS_CONFIG_NAME default "bk4r1" diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index e1340c323b..b2b12e4519 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -16,13 +16,17 @@ #include <common.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> +#include <fdt_support.h> #include <fsl_esdhc.h> +#include <jffs2/load_kernel.h> #include <linux/sizes.h> #include <mmc.h> #include <miiphy.h> +#include <mtd_node.h> #include <netdev.h> #include <power/pmic.h> #include <power/rn5t567_pmic.h> +#include <usb.h> #include <usb/ehci-ci.h> #include "../common/tdx-common.h" @@ -46,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR; #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) +#define USB_CDET_GPIO IMX_GPIO_NR(7, 14) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -71,6 +77,12 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#ifdef CONFIG_USB_EHCI_MX7 +static iomux_v3_cfg_t const usb_cdet_pads[] = { + MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + #ifdef CONFIG_NAND_MXS static iomux_v3_cfg_t const gpmi_pads[] = { MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -319,6 +331,11 @@ int board_init(void) setup_lcd(); #endif +#ifdef CONFIG_USB_EHCI_MX7 + imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); + gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); +#endif + return 0; } @@ -359,6 +376,22 @@ int power_init_board(void) /* set judge and press timer of N_OE to minimal values */ pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); + /* configure sleep slot for 3.3V Ethernet */ + reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT); + reg = (reg & 0xf0) | reg >> 4; + pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg); + + /* disable DCDC2 discharge to avoid backfeeding through VFB2 */ + pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0); + + /* configure sleep slot for ARM rail */ + reg = pmic_reg_read(dev, RN5T567_DC2_SLOT); + reg = (reg & 0xf0) | reg >> 4; + pmic_reg_write(dev, RN5T567_DC2_SLOT, reg); + + /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */ + pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0); + return 0; } @@ -391,6 +424,16 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_FDT_FIXUP_PARTITIONS) + static struct node_info nodes[] = { + { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + }; + + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + return ft_common_board_setup(blob, bd); } #endif @@ -417,4 +460,18 @@ int board_ehci_hcd_init(int port) } return 0; } + +int board_usb_phy_mode(int port) +{ + switch (port) { + case 0: + if (gpio_get_value(USB_CDET_GPIO)) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + case 1: + default: + return USB_INIT_HOST; + } +} #endif diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig index bf9bb0146e..5f7129dd35 100644 --- a/board/toradex/colibri_vf/Kconfig +++ b/board/toradex/colibri_vf/Kconfig @@ -1,17 +1,11 @@ if TARGET_COLIBRI_VF -config SYS_CPU - default "armv7" - config SYS_BOARD default "colibri_vf" config SYS_VENDOR default "toradex" -config SYS_SOC - default "vf610" - config SYS_CONFIG_NAME default "colibri_vf" diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig index 5dafa3822a..6df4134286 100644 --- a/board/tqc/tqma6/Kconfig +++ b/board/tqc/tqma6/Kconfig @@ -22,6 +22,12 @@ config TQMA6Q help select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM +config TQMA6DL + bool "TQMa6DL" + select MX6DL + help + select TQMa6DL with i.MX6DL and 1GiB DRAM + config TQMA6S bool "TQMa6S" select MX6S @@ -70,6 +76,7 @@ endchoice config IMX_CONFIG default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q + default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S endif diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README index 2c012e7b75..c47cb21eeb 100644 --- a/board/tqc/tqma6/README +++ b/board/tqc/tqma6/README @@ -21,6 +21,7 @@ To build U-Boot for the TQ Systems TQMa6 modules: x is a placeholder for the CPU variant q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D) +dl - means i.MX6DL: TQMa6DL (i.MX6DL) s - means i.MX6S: TQMa6S (i.MX6S) baseboard is a placeholder for the boot device @@ -31,5 +32,7 @@ This gives the following configurations: tqma6q_mba6_mmc_config tqma6q_mba6_spi_config +tqma6dl_mba6_mmc_config +tqma6dl_mba6_spi_config tqma6s_mba6_mmc_config tqma6s_mba6_spi_config diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index c8fc95d52b..fdb0fa11b0 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -47,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) int dram_init(void) @@ -232,25 +232,27 @@ static const char *tqma6_get_boardname(void) }; } -int board_late_init(void) +/* setup board specific PMIC */ +int power_init_board(void) { struct pmic *p; - u32 reg; - - setenv("board_name", tqma6_get_boardname()); + u32 reg, rev; - /* - * configure PFUZE100 PMIC: - * TODO: should go to power_init_board if bus switching is - * fixed in generic power code - */ power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS); p = pmic_get("PFUZE100"); if (p && !pmic_probe(p)) { pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + pmic_reg_read(p, PFUZE100_REVID, &rev); + printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev); } + return 0; +} + +int board_late_init(void) +{ + setenv("board_name", tqma6_get_boardname()); + tqma6_bb_board_late_init(); return 0; @@ -267,8 +269,15 @@ int checkboard(void) * Device Tree Support */ #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#define MODELSTRLEN 32u int ft_board_setup(void *blob, bd_t *bd) { + char modelstr[MODELSTRLEN]; + + snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(), + tqma6_bb_get_boardname()); + do_fixup_by_path_string(blob, "/", "model", modelstr); + fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size); /* bring in eMMC dsr settings */ do_fixup_by_path_u32(blob, "/soc/aips-bus@02100000/usdhc@02198000", diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c index 4db1a0bb7d..43349ade1d 100644 --- a/board/tqc/tqma6/tqma6_mba6.c +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -51,22 +51,22 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#if defined(CONFIG_MX6Q) +#if defined(CONFIG_TQMA6Q) #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac -#elif defined(CONFIG_MX6S) +#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 #else -#error "need to define target CPU" +#error "need to select module" #endif @@ -114,6 +114,11 @@ static iomux_v3_cfg_t const mba6_enet_pads[] = { static void mba6_setup_iomuxc_enet(void) { + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* clear gpr1[ENET_CLK_SEL] for externel clock */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, @@ -125,7 +130,7 @@ static void mba6_setup_iomuxc_enet(void) /* Reset PHY */ gpio_direction_output(ENET_PHY_RESET_GPIO , 0); /* Need delay 10ms after power on according to KSZ9031 spec */ - udelay(1000 * 10); + mdelay(10); gpio_set_value(ENET_PHY_RESET_GPIO, 1); /* * KSZ9031 manual: 100 usec wait time after reset before communication @@ -133,7 +138,7 @@ static void mba6_setup_iomuxc_enet(void) * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on * reset before the phy sees a high level */ - udelay(200); + mdelay(15); } static iomux_v3_cfg_t const mba6_uart2_pads[] = { @@ -234,39 +239,20 @@ static void mba6_setup_i2c(void) printf("setup I2C1 failed: %d\n", ret); } - -static iomux_v3_cfg_t const mba6_ecspi1_pads[] = { - NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL), -}; - -static unsigned const mba6_ecspi1_cs[] = { - IMX_GPIO_NR(3, 24), - IMX_GPIO_NR(3, 25), -}; - -static void mba6_setup_iomuxc_spi(void) -{ - unsigned i; - - for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i) - gpio_direction_output(mba6_ecspi1_cs[i], 1); - imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads, - ARRAY_SIZE(mba6_ecspi1_pads)); -} - int board_phy_config(struct phy_device *phydev) { /* * optimized pad skew values depends on CPU variant on the TQMa6x module: - * i.MX6Q/D or i.MX6DL/S + * CONFIG_TQMA6Q: i.MX6Q/D + * CONFIG_TQMA6S: i.MX6S + * CONFIG_TQMA6DL: i.MX6DL */ -#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q) +#if defined(CONFIG_TQMA6Q) #define MBA6X_KSZ9031_CTRL_SKEW 0x0032 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff #define MBA6X_KSZ9031_RX_SKEW 0x3333 #define MBA6X_KSZ9031_TX_SKEW 0x2036 -#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) #define MBA6X_KSZ9031_CTRL_SKEW 0x0030 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff #define MBA6X_KSZ9031_RX_SKEW 0x3333 @@ -341,7 +327,6 @@ int tqma6_bb_board_early_init_f(void) int tqma6_bb_board_init(void) { mba6_setup_i2c(); - mba6_setup_iomuxc_spi(); /* do it here - to have reset completed */ mba6_setup_iomuxc_enet(); diff --git a/board/tqc/tqma6/tqma6dl.cfg b/board/tqc/tqma6/tqma6dl.cfg new file mode 100644 index 0000000000..716033f3fb --- /dev/null +++ b/board/tqc/tqma6/tqma6dl.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2014 - 2015 Markus Niebel <Markus.Niebel@tq-group.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include <config.h> + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6DL DDR config Rev. 0100E */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" |