x86: ich6-gpio: Add Intel Tunnel Creek GPIO support

Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

3 files changed, 7 insertions, 2 deletions

diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
index b260f9a163..154faf6239 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -16,7 +16,7 @@ int arch_early_init_r(void)
 	return 0;
 }
 
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
 {
 	return;
 }
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 4d95c1c927..9978e92006 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -125,7 +125,7 @@ int board_early_init_f(void)
 	return 0;
 }
 
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
 {
 	/* GPIO Set 1 */
 	if (gpio->set1.level)
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 8c6df98bf7..54670d3ac7 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -19,3 +19,8 @@ int board_early_init_f(void)
 
 	return 0;
 }
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+	return;
+}