diff options
| author | Robert Beckett <bob.beckett@collabora.com> | 2020-01-31 15:08:01 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-02-09 21:47:20 +0100 |
| commit | a707281a00f9289175d48c426c3125d63edcc609 (patch) | |
| tree | 04dd9e47cc440897fbb83cc1ab3c931df9a1ffb7 /board | |
| parent | 2d1ea19b551023bfd14629cdf38718c8e7e57f26 (diff) | |
| download | u-boot-a707281a00f9289175d48c426c3125d63edcc609.tar.gz | |
board: ge: bx50v3: use DM for uart
Remove legacy uart pad and iomux code
Enable DM serial and mxc uart
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/ge/bx50v3/bx50v3.c | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index a29fc42d5a..69cd0a1bc7 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -48,10 +48,6 @@ static struct vpd_cache vpd; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS) -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) @@ -74,24 +70,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const uart3_pads[] = { - MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - static int mx6_rgmii_rework(struct phy_device *phydev) { /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ @@ -425,8 +403,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); - setup_iomux_uart(); - #if defined(CONFIG_VIDEO_IPUV3) /* Set LDB clock to Video PLL */ select_ldb_di_clock_source(MXC_PLL5_CLK); |