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authorFabio Estevam <fabio.estevam@nxp.com>2016-01-05 17:02:54 -0200
committerStefano Babic <sbabic@denx.de>2016-01-07 17:47:33 +0100
commit59a6ca54f5db0f3d99ca3bc581ccadc6019e5034 (patch)
tree8740c4e3f095bc4d1bc6b509899fd7cea9a672fa /board/wandboard
parenta307760ab48b428f4c2ac8b5676b29c56eee9f82 (diff)
downloadu-boot-59a6ca54f5db0f3d99ca3bc581ccadc6019e5034.tar.gz
wandboard: Simplify the Ethernet PHY configuration
As per the AR8031 datasheet: "For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." So do as suggested and also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros 8031 PHY driver can be loaded automatically. This results in a simpler code. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'board/wandboard')
-rw-r--r--board/wandboard/wandboard.c36
1 files changed, 2 insertions, 34 deletions
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 0af63d291f..ac001edf3a 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -121,8 +121,9 @@ static void setup_iomux_enet(void)
/* Reset AR8031 PHY */
gpio_direction_output(ETH_PHY_RESET, 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(ETH_PHY_RESET, 1);
+ udelay(100);
}
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
@@ -187,39 +188,6 @@ int board_mmc_init(bd_t *bis)
return 0;
}
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
#if defined(CONFIG_VIDEO_IPUV3)
struct i2c_pads_info mx6q_i2c2_pad_info = {
.scl = {