diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-02-08 18:42:04 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-04-13 20:30:08 +0200 |
| commit | 0b2bd9fedaaa04d370bfeb08d8acbfc65ac39d35 (patch) | |
| tree | 0f1118899d1b6b8358c0c90aa3d570817177a559 /board/toradex/colibri_imx6/clocks.cfg | |
| parent | 15c41a8d9e3d7162f28af7dde94246bf2bb53111 (diff) | |
| download | u-boot-0b2bd9fedaaa04d370bfeb08d8acbfc65ac39d35.tar.gz | |
colibri_imx6: get rid of obsolete nospl configurations
Now with SPL long since being in place even for recovery using SDP
finally get rid of those nospl configurations.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'board/toradex/colibri_imx6/clocks.cfg')
| -rw-r--r-- | board/toradex/colibri_imx6/clocks.cfg | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg deleted file mode 100644 index 1bcbc4fa38..0000000000 --- a/board/toradex/colibri_imx6/clocks.cfg +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb |