powerpc: remove 4xx support

There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>

7 files changed, 0 insertions, 403 deletions

diff --git a/board/t3corp/Kconfig b/board/t3corp/Kconfig
deleted file mode 100644
index 82ed4c95b8..0000000000
--- a/board/t3corp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_T3CORP
-
-config SYS_BOARD
-	default "t3corp"
-
-config SYS_CONFIG_NAME
-	default "t3corp"
-
-endif
diff --git a/board/t3corp/MAINTAINERS b/board/t3corp/MAINTAINERS
deleted file mode 100644
index eaf28c4a9d..0000000000
--- a/board/t3corp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-T3CORP BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/t3corp/
-F:	include/configs/t3corp.h
-F:	configs/t3corp_defconfig
diff --git a/board/t3corp/Makefile b/board/t3corp/Makefile
deleted file mode 100644
index 928d895d50..0000000000
--- a/board/t3corp/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= t3corp.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y += init.o
diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c
deleted file mode 100644
index 3a6c514138..0000000000
--- a/board/t3corp/chip_config.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"600-67", "CPU: 600 PLB: 200 OPB:  67 EBC:  67",
-		{
-			0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"667", "CPU: 667 PLB: 166 OPB:  83 EBC:  83",
-		{
-			0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
-			0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1000", "CPU:1000 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1066", "CPU:1066 PLB: 266 OPB:  88 EBC:  88",
-		{
-			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/t3corp/config.mk b/board/t3corp/config.mk
deleted file mode 100644
index f7ac7558d0..0000000000
--- a/board/t3corp/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/t3corp/init.S b/board/t3corp/init.S
deleted file mode 100644
index 7ae9c43924..0000000000
--- a/board/t3corp/init.S
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- */
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
-	 * use the speed up boot process. It is patched after relocation to
-	 * enable SA_I
-	 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
-		 CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the DDR(2) detection
-	 * routine.
-	 */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
-		 AC_RWX | SA_G)
-#endif
-
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
-		 AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
-		 AC_RW | SA_IG)
-
-	/* PCIe UTL register */
-	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
-
-	/* TLB-entry for FPGA(s) */
-	tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
-		 CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
-		 AC_RW | SA_IG)
-
-	/* TLB-entry for OCM */
-	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
-		 AC_RWX | SA_I)
-
-	/* TLB-entry for Local Configuration registers => peripherals */
-	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
-		 CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
-
-	tlbtab_end
diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c
deleted file mode 100644
index 586c6f9a62..0000000000
--- a/board/t3corp/t3corp.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc440.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <mtd/cfi_flash.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/4xx_pcie.h>
-#include <asm/ppc4xx-gpio.h>
-
-int board_early_init_f(void)
-{
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0x7fffffff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC3ER, 0x00000000);	/* disable all */
-	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 * enable GPIO 49-63
-	 * UART0: 4 pins
-	 */
-	mtsdr(SDR0_PFC0, 0x00007fff);
-	mtsdr(SDR0_PFC1, 0x00040000);
-
-	/* Enable PCI host functionality in SDR0_PCI0 */
-	mtsdr(SDR0_PCI0, 0xe0000000);
-
-	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
-
-	/* Setup PLB4-AHB bridge based on the system address map */
-	mtdcr(AHB_TOP, 0x8000004B);
-	mtdcr(AHB_BOT, 0x8000004B);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: T3CORP");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	/*
-	 * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
-	 * boot EBC mapping only supports a maximum of 16MBytes
-	 * (4.ff00.0000 - 4.ffff.ffff).
-	 * To solve this problem, the flash has to get remapped to another
-	 * EBC address which accepts bigger regions:
-	 *
-	 * 0xfn00.0000 -> 4.cn00.0000
-	 */
-
-	/* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
-	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
-	      EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
-
-	/* Remove TLB entry of boot EBC mapping */
-	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
-
-	/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
-	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
-		    CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
-
-	/*
-	 * Now accessing of the whole 64Mbytes of NOR flash at virtual address
-	 * 0xfc00.0000 is possible
-	 */
-
-	/*
-	 * Clear potential errors resulting from auto-calibration.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 sdr0_srst1 = 0;
-	u32 eth_cfg;
-
-	/*
-	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
-	 * This is board specific, so let's do it here.
-	 */
-	mfsdr(SDR0_ETH_CFG, eth_cfg);
-	/* disable SGMII mode */
-	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
-		     SDR0_ETH_CFG_SGMII1_ENABLE |
-		     SDR0_ETH_CFG_SGMII0_ENABLE);
-	/* Set the for 2 RGMII mode */
-	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
-	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
-	eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
-	mtsdr(SDR0_ETH_CFG, eth_cfg);
-
-	/*
-	 * The AHB Bridge core is held in reset after power-on or reset
-	 * so enable it now
-	 */
-	mfsdr(SDR0_SRST1, sdr0_srst1);
-	sdr0_srst1 &= ~SDR0_SRST1_AHB;
-	mtsdr(SDR0_SRST1, sdr0_srst1);
-
-	return 0;
-}
-
-int board_pcie_last(void)
-{
-	/*
-	 * Only PCIe0 for now, PCIe1 hangs on this board
-	 */
-	return 0;
-}
-
-/*
- * Board specific WRDTR and CLKTR values used by the auto-
- * calibration code (4xx_ibm_ddr2_autocalib.c).
- */
-static struct sdram_timing board_scan_options[] = {
-	{1, 2},
-	{-1, -1}
-};
-
-struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
-{
-	return board_scan_options;
-}
-
-/*
- * Accessor functions replacing the "weak" functions in
- * drivers/mtd/cfi_flash.c
- *
- * The NOR flash devices "behind" the FPGA's (Xilinx DS617)
- * can only be read correctly in 16bit mode. We need to emulate
- * 8bit and 32bit reads here in the board specific code.
- */
-u8 flash_read8(void *addr)
-{
-	u16 val = __raw_readw((void *)((u32)addr & ~1));
-
-	if ((u32)addr & 1)
-		return val;
-
-	return val >> 8;
-}
-
-u32 flash_read32(void *addr)
-{
-	return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
-}
-
-void flash_cmd_reset(flash_info_t *info)
-{
-	/*
-	 * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
-	 * needs the Spansion type reset commands. The other flash chip
-	 * is located behind a FPGA (Xilinx DS617) and needs the Intel type
-	 * reset command.
-	 */
-	if (info->start[0] == CONFIG_SYS_FLASH_BASE)
-		flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
-	else
-		flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-}