summaryrefslogtreecommitdiff
path: root/board/logicpd
diff options
context:
space:
mode:
authorAdam Ford <aford173@gmail.com>2019-07-01 09:33:39 -0500
committerTom Rini <trini@konsulko.com>2019-07-27 13:36:52 -0400
commit02acbb9472e0e981c3e4b33357723258b2468405 (patch)
tree4cb037942f9f717f2b6009e8e0eab3eda3dfee6f /board/logicpd
parentc94703483c694aebc5617e4b1975803010f815e7 (diff)
downloadu-boot-02acbb9472e0e981c3e4b33357723258b2468405.tar.gz
ARM: am3517_evm: Fix pin muxing to enable EHCI Host in the future
This patch enables the pinmuxing to support gpio_57 for phy reset and fixes the pinmuxing for the ECHI tranceiver. The clocks don't appear to by fully enabled yet, so OMAP-EHCI on am3517 is still not yet working, but we're one step closer. Signed-off-by: Adam Ford <aford173@gmail.com>
Diffstat (limited to 'board/logicpd')
-rw-r--r--board/logicpd/am3517evm/am3517evm.h26
1 files changed, 13 insertions, 13 deletions
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
index 99a08032e0..0e5b8326ba 100644
--- a/board/logicpd/am3517evm/am3517evm.h
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -111,7 +111,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) \
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
@@ -339,18 +339,18 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
/* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \